Assessing NUMA performance based on hardware event counters
- Cost models play an important role for the efficient implementation of software systems. These models can be embedded in operating systems and execution environments to optimize execution at run time. Even though non-uniform memory access (NUMA) architectures are dominating today's server landscape, there is still a lack of parallel cost models that represent NUMA system sufficiently. Therefore, the existing NUMA models are analyzed, and a two-step performance assessment strategy is proposed that incorporates low-level hardware counters as performance indicators. To support the two-step strategy, multiple tools are developed, all accumulating and enriching specific hardware event counter information, to explore, measure, and visualize these low-overhead performance indicators. The tools are showcased and discussed alongside specific experiments in the realm of performance assessment.
Verfasserangaben: | Max PlauthORCiDGND, Christoph Sterz, Felix Eberhardt, Frank FeinbubeGND, Andreas PolzeORCiDGND |
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DOI: | https://doi.org/10.1109/IPDPSW.2017.51 |
ISBN: | 978-0-7695-6149-3 |
ISSN: | 2164-7062 |
Titel des übergeordneten Werks (Englisch): | IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Verlag: | Institute of Electrical and Electronics Engineers |
Verlagsort: | New York |
Publikationstyp: | Sonstiges |
Sprache: | Englisch |
Datum der Erstveröffentlichung: | 24.08.2017 |
Erscheinungsjahr: | 2017 |
Datum der Freischaltung: | 08.09.2022 |
Freies Schlagwort / Tag: | Memory management; Parallel programming; Performance analysis |
Seitenanzahl: | 10 |
Erste Seite: | 904 |
Letzte Seite: | 913 |
Organisationseinheiten: | An-Institute / Hasso-Plattner-Institut für Digital Engineering gGmbH |
DDC-Klassifikation: | 0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 000 Informatik, Informationswissenschaft, allgemeine Werke |
Peer Review: | Referiert |