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Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction
(1998)
The family of default logics
(1998)
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
(1999)
A method of construction of combinational self-checking units with detection of all single faults
(1999)
In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks