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Soft error detection and correction architecture for asynchronous bundled data designs
- In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. TwoIn this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%.…
Author details: | Felipe A. KuentzerORCiD, Miloš KrstićORCiDGND |
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DOI: | https://doi.org/10.1109/TCSI.2020.2998911 |
ISSN: | 1549-8328 |
ISSN: | 1558-0806 |
Title of parent work (English): | IEEE transactions on circuits and systems |
Publisher: | Institute of Electrical and Electronics Engineers |
Place of publishing: | New York |
Publication type: | Article |
Language: | English |
Date of first publication: | 2020/06/09 |
Publication year: | 2020 |
Release date: | 2023/03/30 |
Tag: | DMR; Fault tolerance; Fault tolerant systems; TMR; asynchrounous design; bundled data; circuit Faults; click controller; clocks; concurrent checking; latches; self-checking; soft errors; timing; transient Faults; transient analysis |
Volume: | 67 |
Issue: | 12 |
Number of pages: | 12 |
First page: | 4883 |
Last Page: | 4894 |
Funding institution: | DFG-Project ENROLGerman Research Foundation (DFG) [KR 4346/2-1] |
Organizational units: | Mathematisch-Naturwissenschaftliche Fakultät / Institut für Informatik und Computational Science |
DDC classification: | 0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 000 Informatik, Informationswissenschaft, allgemeine Werke |
6 Technik, Medizin, angewandte Wissenschaften / 62 Ingenieurwissenschaften / 620 Ingenieurwissenschaften und zugeordnete Tätigkeiten | |
Peer review: | Referiert |