• search hit 4 of 5
Back to Result List

Handling of transient and permanent faults in dynamically scheduled super-scalar processors

  • This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.

Export metadata

Additional Services

Search Google Scholar Statistics
Metadaten
Author details:Felix MühlbauerORCiD, Lukas Schröder, Mario SchölzelORCiDGND
DOI:https://doi.org/10.1016/j.microrel.2017.11.021
ISSN:0026-2714
Title of parent work (English):Microelectronics reliability
Publisher:Elsevier
Place of publishing:Oxford
Publication type:Article
Language:English
Date of first publication:2017/12/22
Publication year:2018
Release date:2022/04/04
Tag:Dynamically scheduled processor; Fail-safe; Fault tolerance
Volume:80
Number of pages:8
First page:176
Last Page:183
Organizational units:Humanwissenschaftliche Fakultät / Strukturbereich Bildungswissenschaften / Department Grundschulpädagogik
DDC classification:3 Sozialwissenschaften / 37 Bildung und Erziehung / 370 Bildung und Erziehung
Accept ✔
This website uses technically necessary session cookies. By continuing to use the website, you agree to this. You can find our privacy policy here.