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The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.
In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.