Institut für Informatik und Computational Science
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An asymptotic analysis and improvement of AdaBoost in the binary classification case (in Japanese)
(2000)
Graded paraconsistency
(2000)
Grundlagen digitaler Systeme
(2000)
The objective of this thesis is to provide new space compaction techniques for testing or concurrent checking of digital circuits. In particular, the work focuses on the design of space compactors that achieve high compaction ratio and minimal loss of testability of the circuits. In the first part, the compactors are designed for combinational circuits based on the knowledge of the circuit structure. Several algorithms for analyzing circuit structures are introduced and discussed for the first time. The complexity of each design procedure is linear with respect to the number of gates of the circuit. Thus, the procedures are applicable to large circuits. In the second part, the first structural approach for output compaction for sequential circuits is introduced. Essentially, it enhances the first part. For the approach introduced in the third part it is assumed that the structure of the circuit and the underlying fault model are unknown. The space compaction approach requires only the knowledge of the fault-free test responses for a precomputed test set. The proposed compactor design guarantees zero-aliasing with respect to the precomputed test set.
Significant inferences
(2000)
Maximal solid codes
(1999)
Workshop on Implementing Automata : WIA99 - pre-proceedings ; Potsdam, Germany, 17 - 19. July 1999
(1999)
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
(1999)
A method of construction of combinational self-checking units with detection of all single faults
(1999)
Towards computer science
(1998)
Fault-tolerant self-dual circuits with error detection by parity- and group parity prediction
(1998)
Compressions and extensions
(1998)