On hardware-based fault-handling in dynamically scheduled processors
- This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.
Author details: | Felix MühlbauerORCiD, Lukas Schröder, Mario SchölzelORCiDGND |
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DOI: | https://doi.org/10.1109/DDECS.2017.7934572 |
ISBN: | 978-1-5386-0472-4 |
ISSN: | 2334-3133 |
ISSN: | 2473-2117 |
Title of parent work (English): | 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2017 |
Publisher: | IEEE |
Place of publishing: | New York |
Publication type: | Other |
Language: | English |
Date of first publication: | 2017/05/29 |
Publication year: | 2017 |
Release date: | 2022/11/18 |
Number of pages: | 6 |
First page: | 201 |
Last Page: | 206 |
Organizational units: | Mathematisch-Naturwissenschaftliche Fakultät / Institut für Informatik und Computational Science |
DDC classification: | 0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 000 Informatik, Informationswissenschaft, allgemeine Werke |