Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture
- The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication and the required process synchronization can be realized on a non-cache-coherent many-core CPU. The Intel Single-chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message-based approach and reveals a reduction of the communication costs for the NAS Parallel Benchmarks 3-D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non-cache-coherent architectures.
Author details: | Steffen ChristgauORCiDGND, Bettina SchnorORCiDGND |
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DOI: | https://doi.org/10.1002/cpe.4113 |
ISSN: | 1532-0626 |
ISSN: | 1532-0634 |
Title of parent work (English): | Concurrency and computation : practice & experience |
Publisher: | Wiley |
Place of publishing: | Hoboken |
Publication type: | Article |
Language: | English |
Year of first publication: | 2017 |
Publication year: | 2017 |
Release date: | 2020/04/20 |
Tag: | MPI; one-sided communication; programming models and systems for many-cores; software-managed cache coherence; synchronization |
Volume: | 29 |
Number of pages: | 15 |
Peer review: | Referiert |
Institution name at the time of the publication: | Mathematisch-Naturwissenschaftliche Fakultät / Institut für Informatik |