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Full error detection and correction method applied on pipelined structure using two approaches

  • In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multipleIn this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.zeige mehrzeige weniger

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Metadaten
Verfasserangaben:Mehmed DugORCiD, Stefan Weidling, Egor Sogomonyan, Dejan Jokic, Miloš KrstićORCiDGND
DOI:https://doi.org/10.1142/S0218126620502187
ISSN:0218-1266
ISSN:1793-6454
Titel des übergeordneten Werks (Englisch):Journal of circuits, systems and computers
Verlag:World Scientific
Verlagsort:Singapore
Publikationstyp:Wissenschaftlicher Artikel
Sprache:Englisch
Datum der Erstveröffentlichung:04.03.2020
Erscheinungsjahr:2020
Datum der Freischaltung:15.05.2023
Freies Schlagwort / Tag:EDC; FEDC; Fault tolerance
Band:29
Ausgabe:13
Aufsatznummer:2050218
Seitenanzahl:15
Organisationseinheiten:Mathematisch-Naturwissenschaftliche Fakultät / Institut für Informatik und Computational Science
DDC-Klassifikation:0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 000 Informatik, Informationswissenschaft, allgemeine Werke
Peer Review:Referiert
Lizenz (Deutsch):License LogoKeine öffentliche Lizenz: Unter Urheberrechtsschutz
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