TY  - JOUR
A1  - Rabenalt, Thomas
A1  - Richter, Michael
A1  - Pöhl, Frank
A1  - Gössel, Michael
T1  - Highly efficient test response compaction using a hierarchical x-masking technique
JF  - IEEE transactions on computer-aided design of integrated circuits and systems
N2  - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.
KW  - Design for testability (DFT)
KW  - test response compaction
KW  - X-masking
KW  - X-values
Y1  - 2012
U6  - https://doi.org/10.1109/TCAD.2011.2181847
SN  - 0278-0070
VL  - 31
IS  - 6
SP  - 950
EP  - 957
PB  - Inst. of Electr. and Electronics Engineers
CY  - Piscataway
ER  - 
TY  - THES
A1  - Richter, Michael
T1  - Anwendung nichtlinearer Codes zur Fehlererkennung und -korrektur
Y1  - 2011
CY  - Potsdam
ER  - 
TY  - JOUR
A1  - Hilscher, Martin
A1  - Braun, Michael
A1  - Richter, Michael
A1  - Leininger, Andreas
A1  - Gössel, Michael
T1  - X-tolerant test data compaction with accelerated shift registers
N2  - Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.
Y1  - 2009
UR  - http://www.springerlink.com/content/100286
U6  - https://doi.org/10.1007/s10836-009-5107-5
SN  - 0923-8174
ER  -