TY - JOUR A1 - Kuentzer, Felipe A. A1 - Juracy, Leonardo R. A1 - Moreira, Matheus T. A1 - Amory, Alexandre M. T1 - Testing the blade resilient asynchronous template JF - Analog integrated circuits and signal processing : an international journal N2 - As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on the other hand, have the potential to improve energy efficiency and performance. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. This paper demonstrates that scan chains can be prohibitive for Blade due to their high silicon costs., which can reach more than 100%. Then, it proposes an alternative test approach that allows concurrent testing, stuck-at, and delay testing. The test approach is based on the reuse the Blade features to provide testability, with silicon area overheads between 4 and 7%. KW - asynchronous design KW - blade KW - delay faults KW - design for Testability KW - stuck-at faults KW - timing resilient design Y1 - 2020 U6 - https://doi.org/10.1007/s10470-020-01651-8 SN - 0925-1030 SN - 1573-1979 VL - 106 IS - 1 SP - 219 EP - 234 PB - Springer CY - Dordrecht ER - TY - JOUR A1 - Kuentzer, Felipe A. A1 - Krstić, Miloš T1 - Soft error detection and correction architecture for asynchronous bundled data designs JF - IEEE transactions on circuits and systems N2 - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%. KW - circuit Faults KW - latches KW - Fault tolerance KW - Fault tolerant systems KW - timing KW - clocks KW - transient analysis KW - asynchrounous design KW - soft errors KW - transient Faults KW - bundled data KW - click controller KW - self-checking KW - concurrent checking KW - DMR KW - TMR Y1 - 2020 U6 - https://doi.org/10.1109/TCSI.2020.2998911 SN - 1549-8328 SN - 1558-0806 VL - 67 IS - 12 SP - 4883 EP - 4894 PB - Institute of Electrical and Electronics Engineers CY - New York ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Marjanovic, Milos A1 - Drasko, Bojan A1 - Calligaro, Cristiano A1 - Schrape, Oliver A1 - Gatti, Umberto A1 - Kuentzer, Felipe A. A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Krstić, Miloš T1 - Analysis of single event transient effects in standard delay cells based on decoupling capacitors JF - Journal of circuits, systems, and computers : JCSC N2 - Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter. KW - single event transients KW - standard delay cells KW - decoupling capacitors Y1 - 2022 U6 - https://doi.org/10.1142/S0218126622400072 SN - 0218-1266 SN - 1793-6454 VL - 31 IS - 18 PB - World Scientific CY - Singapore [u.a.] ER -