TY  - GEN
A1  - Plauth, Max
A1  - Sterz, Christoph
A1  - Eberhardt, Felix
A1  - Feinbube, Frank
A1  - Polze, Andreas
T1  - Assessing NUMA performance based on hardware event counters
T2  - IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
N2  - Cost models play an important role for the efficient implementation of software systems. These models can be embedded in operating systems and execution environments to optimize execution at run time. Even though non-uniform memory access (NUMA) architectures are dominating today's server landscape, there is still a lack of parallel cost models that represent NUMA system sufficiently. Therefore, the existing NUMA models are analyzed, and a two-step performance assessment strategy is proposed that incorporates low-level hardware counters as performance indicators. To support the two-step strategy, multiple tools are developed, all accumulating and enriching specific hardware event counter information, to explore, measure, and visualize these low-overhead performance indicators. The tools are showcased and discussed alongside specific experiments in the realm of performance assessment.
KW  - Parallel programming
KW  - Performance analysis
KW  - Memory management
Y1  - 2017
SN  - 978-0-7695-6149-3
U6  - https://doi.org/10.1109/IPDPSW.2017.51
SN  - 2164-7062
SP  - 904
EP  - 913
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  -