TY  - JOUR
A1  - Christgau, Steffen
A1  - Schnor, Bettina
T1  - Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture
JF  - Concurrency and computation : practice & experience
N2  - The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication and the required process synchronization can be realized on a non-cache-coherent many-core CPU. The Intel Single-chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message-based approach and reveals a reduction of the communication costs for the NAS Parallel Benchmarks 3-D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non-cache-coherent architectures.
KW  - MPI
KW  - one-sided communication
KW  - programming models and systems for many-cores
KW  - synchronization
KW  - software-managed cache coherence
Y1  - 2017
U6  - https://doi.org/10.1002/cpe.4113
SN  - 1532-0626
SN  - 1532-0634
VL  - 29
PB  - Wiley
CY  - Hoboken
ER  -