@article{MuehlbauerSchroederSchoelzel2018,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario},
  title     = {Handling of transient and permanent faults in dynamically scheduled super-scalar processors},
  series = {Microelectronics reliability},
  volume    = {80},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2017.11.021},
  pages     = {176 -- 183},
  year      = {2018},
  abstract  = {This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.},
  language  = {en}
}
@misc{MuehlbauerSchroederSchoelzel2017,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario},
  title     = {On hardware-based fault-handling in dynamically scheduled processors},
  series = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017},
  journal   = {20th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS) 2017},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-0472-4},
  issn      = {2334-3133},
  doi       = {10.1109/DDECS.2017.7934572},
  pages     = {201 -- 206},
  year      = {2017},
  abstract  = {This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach.},
  language  = {en}
}
@misc{MuehlbauerSchroederSkoncejetal.2017,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Skoncej, Patryk and Sch{\"o}lzel, Mario},
  title     = {Handling manufacturing and aging faults with software-based techniques in tiny embedded systems},
  series = {18th IEEE Latin American Test Symposium (LATS 2017)},
  journal   = {18th IEEE Latin American Test Symposium (LATS 2017)},
  publisher = {IEEE},
  address   = {New York},
  isbn      = {978-1-5386-0415-1},
  doi       = {10.1109/LATW.2017.7906756},
  pages     = {6},
  year      = {2017},
  abstract  = {Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts.},
  language  = {en}
}