@phdthesis{Wist2011,
  author    = {Wist, Dominic},
  title     = {Attacking complexity in logic synthesis of asynchronous circuits},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-59706},
  school      = {Universit{\"a}t Potsdam},
  year      = {2011},
  abstract  = {Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous counterparts. A driving force for a widespread use of asynchronous technology is the availability of mature EDA (Electronic Design Automation) tools which provide an entire automated design flow starting from an HDL (Hardware Description Language) specification yielding the final circuit layout. Even though there was much progress in developing such EDA tools for asynchronous circuit design during the last two decades, the maturity level as well as the acceptance of them is still not comparable with tools for synchronous circuit design. In particular, logic synthesis (which implies the application of Boolean minimisation techniques) for the entire system's control path can significantly improve the efficiency of the resulting asynchronous implementation, e.g. in terms of chip area and performance. However, logic synthesis, in particular for asynchronous circuits, suffers from complexity problems. Signal Transitions Graphs (STGs) are labelled Petri nets which are a widely used to specify the interface behaviour of speed independent (SI) circuits - a robust subclass of asynchronous circuits. STG decomposition is a promising approach to tackle complexity problems like state space explosion in logic synthesis of SI circuits. The (structural) decomposition of STGs is guided by a partition of the output signals and generates a usually much smaller component STG for each partition member, i.e. a component STG with a much smaller state space than the initial specification. However, decomposition can result in component STGs that in isolation have so-called irreducible CSC conflicts (i.e. these components are not SI synthesisable anymore) even if the specification has none of them. A new approach is presented to avoid such conflicts by introducing internal communication between the components. So far, STG decompositions are guided by the finest output partitions, i.e. one output per component. However, this might not yield optimal circuit implementations. Efficient heuristics are presented to determine coarser partitions leading to improved circuits in terms of chip area. For the new algorithms correctness proofs are given and their implementations are incorporated into the decomposition tool DESIJ. The presented techniques are successfully applied to some benchmarks - including 'real-life' specifications arising in the context of control resynthesis - which delivered promising results.},
  language  = {en}
}
@article{WistWollowskiSchaeferetal.2009,
  author    = {Wist, Dominic and Wollowski, Ralf and Schaefer, Mark and Vogler, Walter},
  title     = {Avoiding irreducible CSC conflicts by internal communication},
  issn      = {0169-2968},
  doi       = {10.3233/Fi-2009-140},
  year      = {2009},
  abstract  = {Resynthesis of handshake specifications obtained e. g. from BALSA or TANGRAM with speed-independent logic synthesis from STGs is a promising approach. To deal with state-space explosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here, we present a new approach to solve such conflicts by introducing internal communication between the components. We give some first, very encouraging results for very large STGs concerning synthesis time and circuit area.},
  language  = {en}
}
@article{WistSchaeferVogleretal.2011,
  author    = {Wist, Dominic and Schaefer, Mark and Vogler, Walter and Wollowski, Ralf},
  title     = {Signal transition graph decomposition internal communication for speed independent circuit implementation},
  series = {IET Computers and digital techniques},
  volume    = {5},
  journal   = {IET Computers and digital techniques},
  number    = {6},
  publisher = {Institution of Engineering and Technology},
  address   = {Hertford},
  issn      = {1751-8601},
  doi       = {10.1049/iet-cdt.2010.0162},
  pages     = {440 -- 451},
  year      = {2011},
  abstract  = {Logic synthesis of speed independent circuits based on signal transition graph (STG) decomposition is a promising approach to tackle complexity problems like state-space explosion. Unfortunately, decomposition can result in components that in isolation have irreducible complete state coding conflicts. In earlier work, the authors showed how to resolve such conflicts by introducing internal communication between components, but only for very restricted specification structures. Here, they improve their former work by presenting algorithms for identifying delay transitions and inserting gyroscopes for specifications having a much more general structure. Thus, the authors are now able to synthesise controllers from real-life specifications. For all algorithms, they present correctness proofs and show their successful application to benchmarks, including very complex STGs arising in the context of control resynthesis.},
  language  = {en}
}
@book{WistWollowski2007,
  author    = {Wist, Dominic and Wollowski, Ralf},
  title     = {STG decomposition : avoiding irreducible CSC conflicts by internal communication},
  isbn      = {978-3-940793-02-7},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-32968},
  publisher      = {Universit{\"a}t Potsdam},
  year      = {2007},
  abstract  = {Inhalt: 1 Introduction 2 Basic Definitions 3 Achieving SI Implementability by Internal Communication 4 Towards a Structural Method 5 Examples 6 Conclusions and Future Work},
  language  = {en}
}
@book{WistSchaeferVogleretal.2010,
  author    = {Wist, Dominic and Schaefer, Mark and Vogler, Walter and Wollowski, Ralf},
  title     = {STG decomposition : internal communication for SI implementability},
  publisher = {Universit{\"a}tsverlag Potsdam},
  address   = {Potsdam},
  isbn      = {978-3-86956-037-3},
  url       = {http://nbn-resolving.de/urn:nbn:de:kobv:517-opus-40786},
  publisher      = {Universit{\"a}t Potsdam},
  pages     = {36},
  year      = {2010},
  abstract  = {STG decomposition is a promising approach to tackle the complexity problems arising in logic synthesis of speed independent circuits, a robust asynchronous (i.e. clockless) circuit type. Unfortunately, STG decomposition can result in components that in isolation have irreducible CSC conflicts. Generalising earlier work, it is shown how to resolve such conflicts by introducing internal communication between the components via structural techniques only.},
  language  = {en}
}