@article{MuehlbauerSchroederSchoelzel2018,
  author    = {M{\"u}hlbauer, Felix and Schr{\"o}der, Lukas and Sch{\"o}lzel, Mario},
  title     = {Handling of transient and permanent faults in dynamically scheduled super-scalar processors},
  series = {Microelectronics reliability},
  volume    = {80},
  journal   = {Microelectronics reliability},
  publisher = {Elsevier},
  address   = {Oxford},
  issn      = {0026-2714},
  doi       = {10.1016/j.microrel.2017.11.021},
  pages     = {176 -- 183},
  year      = {2018},
  abstract  = {This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.},
  language  = {en}
}
@article{KuentzerKrstić2020,
  author    = {Kuentzer, Felipe A. and Krstić, Miloš},
  title     = {Soft error detection and correction architecture for asynchronous bundled data designs},
  series = {IEEE transactions on circuits and systems},
  volume    = {67},
  journal   = {IEEE transactions on circuits and systems},
  number    = {12},
  publisher = {Institute of Electrical and Electronics Engineers},
  address   = {New York},
  issn      = {1549-8328},
  doi       = {10.1109/TCSI.2020.2998911},
  pages     = {4883 -- 4894},
  year      = {2020},
  abstract  = {In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6\% to 17.6\%, and increasing energy efficiency, which can be up to 6.5\%.},
  language  = {en}
}
@article{DugWeidlingSogomonyanetal.2020,
  author    = {Dug, Mehmed and Weidling, Stefan and Sogomonyan, Egor and Jokic, Dejan and Krstić, Miloš},
  title     = {Full error detection and correction method applied on pipelined structure using two approaches},
  series = {Journal of circuits, systems and computers},
  volume    = {29},
  journal   = {Journal of circuits, systems and computers},
  number    = {13},
  publisher = {World Scientific},
  address   = {Singapore},
  issn      = {0218-1266},
  doi       = {10.1142/S0218126620502187},
  pages     = {15},
  year      = {2020},
  abstract  = {In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.},
  language  = {en}
}