@article{ChristgauSchnor2017,
  author    = {Christgau, Steffen and Schnor, Bettina},
  title     = {Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture},
  series = {Concurrency and computation : practice \& experience},
  volume    = {29},
  journal   = {Concurrency and computation : practice \& experience},
  publisher = {Wiley},
  address   = {Hoboken},
  issn      = {1532-0626},
  doi       = {10.1002/cpe.4113},
  pages     = {15},
  year      = {2017},
  abstract  = {The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication and the required process synchronization can be realized on a non-cache-coherent many-core CPU. The Intel Single-chip Cloud Computer serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to 5 times faster than the default message-based approach and reveals a reduction of the communication costs for the NAS Parallel Benchmarks 3-D fast Fourier Transform by a factor of 5. Further, the paper derives conclusions for future non-cache-coherent architectures.},
  language  = {en}
}