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Frequency-domain optimization of digital switching noise based on clock scheduling

  • The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to theThe simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.show moreshow less

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Metadaten
Author:Xin FanORCiD, Mikkel B. Stegmann, Oliver Schrappe, Steffen Zeidler, Isac G. Jensen, Jannich Thorsen, Tobias Bjerregaard, Milos Krstic
DOI:https://doi.org/10.1109/TCSI.2016.2546118
ISSN:1549-8328
Parent Title (English):IEEE Transactions on Circuits and Systems I
Document Type:Article
Language:English
Year of first Publication:2016
Release Date:2019/04/10
Volume:63
Issue:7
First Page:982
Last Page:993
Organizational units:Mathematisch-Naturwissenschaftliche Fakultät / Institut für Physik und Astronomie
Dewey Decimal Classification:0 Informatik, Informationswissenschaft, allgemeine Werke