Towards improving data transfer efficiency for accelerators using hardware compression
- The overhead of moving data is the major limiting factor in todays hardware, especially in heterogeneous systems where data needs to be transferred frequently between host and accelerator memory. With the increasing availability of hardware-based compression facilities in modern computer architectures, this paper investigates the potential of hardware-accelerated I/O Link Compression as a promising approach to reduce data volumes and transfer time, thus improving the overall efficiency of accelerators in heterogeneous systems. Our considerations are focused on On-the-Fly compression in both Single-Node and Scale-Out deployments. Based on a theoretical analysis, this paper demonstrates the feasibility of hardware-accelerated On-the-Fly I/O Link Compression for many workloads in a Scale-Out scenario, and for some even in a Single-Node scenario. These findings are confirmed in a preliminary evaluation using software-and hardware-based implementations of the 842 compression algorithm.
Author details: | Max PlauthORCiDGND, Andreas PolzeORCiDGND |
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DOI: | https://doi.org/10.1109/CANDARW.2018.00031 |
ISBN: | 978-1-5386-9184-7 |
Title of parent work (English): | Sixth International Symposium on Computing and Networking Workshops (CANDARW) |
Publisher: | IEEE |
Place of publishing: | New York |
Publication type: | Other |
Language: | English |
Date of first publication: | 2018/12/27 |
Publication year: | 2018 |
Release date: | 2022/02/21 |
Tag: | Data compression; accelerator architectures; data transfer; hardware |
Number of pages: | 7 |
First page: | 125 |
Last Page: | 131 |
Organizational units: | Digital Engineering Fakultät / Hasso-Plattner-Institut für Digital Engineering GmbH |
DDC classification: | 0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 000 Informatik, Informationswissenschaft, allgemeine Werke |