TY  - JOUR
A1  - Chen, Junchao
A1  - Lange, Thomas
A1  - Andjelkovic, Milos
A1  - Simevski, Aleksandar
A1  - Krstić, Miloš
T1  - Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning
JF  - Microelectronics reliability
N2  - This work introduces an embedded approach for the prediction of Solar Particle Events (SPEs) in space applications by combining the real-time Soft Error Rate (SER) measurement with SRAM-based detector and the offline trained machine learning model. The proposed approach is intended for the self-adaptive fault-tolerant multiprocessing systems employed in space applications. With respect to the state-of-the-art, our solution allows for predicting the SER 1 h in advance and fine-grained hourly tracking of SER variations during SPEs as well as under normal conditions. Therefore, the target system can activate the appropriate mechanisms for radiation hardening before the onset of high radiation levels. Based on the comparison of five different machine learning algorithms trained with the public space flux database, the preliminary results indicate that the best prediction accuracy is achieved with the recurrent neural network (RNN) with long short-term memory (LSTM).
Y1  - 2020
U6  - https://doi.org/10.1016/j.microrel.2020.113799
SN  - 0026-2714
VL  - 114
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - GEN
A1  - Schrape, Oliver
A1  - Balashov, Alexey
A1  - Simevski, Aleksandar
A1  - Benito, Carlos
A1  - Krstić, Miloš
T1  - Master-Clone placement with individual clock tree implementation
BT  - a Case on Physical Chip Design
T2  - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
N2  - A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node.
KW  - Hierarchical Design
KW  - Physical Implementation
KW  - Clock Tree Implementation
Y1  - 2018
SN  - 978-1-5386-7656-1
PB  - IEEE
CY  - New York
ER  -