TY  - JOUR
A1  - Kuentzer, Felipe A.
A1  - Juracy, Leonardo R.
A1  - Moreira, Matheus T.
A1  - Amory, Alexandre M.
T1  - Testing the blade resilient asynchronous template
JF  - Analog integrated circuits and signal processing : an international journal
N2  - As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on the other hand, have the potential to improve energy efficiency and performance. Blade is an asynchronous timing resilient template that leverages the advantages of both asynchronous and timing resilient techniques. However, Blade still presents challenges regarding its testability, which hinders its commercial or large-scale application. This paper demonstrates that scan chains can be prohibitive for Blade due to their high silicon costs., which can reach more than 100%. Then, it proposes an alternative test approach that allows concurrent testing, stuck-at, and delay testing. The test approach is based on the reuse the Blade features to provide testability, with silicon area overheads between 4 and 7%.
KW  - asynchronous design
KW  - blade
KW  - delay faults
KW  - design for Testability
KW  - stuck-at faults
KW  - timing resilient design
Y1  - 2020
U6  - https://doi.org/10.1007/s10470-020-01651-8
SN  - 0925-1030
SN  - 1573-1979
VL  - 106
IS  - 1
SP  - 219
EP  - 234
PB  - Springer
CY  - Dordrecht
ER  -