TY - JOUR A1 - Schrape, Oliver A1 - Andjelkovic, Marko A1 - Breitenreiter, Anselm A1 - Zeidler, Steffen A1 - Balashov, Alexey A1 - Krstić, Miloš T1 - Design and evaluation of radiation-hardened standard cell flip-flops JF - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers N2 - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant. KW - Single event effect KW - fault tolerance KW - triple modular redundancy KW - ASIC KW - design flow KW - radhard design Y1 - 2021 U6 - https://doi.org/10.1109/TCSI.2021.3109080 SN - 1549-8328 SN - 1558-0806 SN - 1057-7122 VL - 68 IS - 11 SP - 4796 EP - 4809 PB - Inst. of Electr. and Electronics Engineers CY - New York, NY ER -