TY  - THES
A1  - Kunz, Wolfgang
T1  - Testing techniques in logic synthesis
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Pradhan, D. K.
A1  - Chatterjee, M.
A1  - Swarna, M.
A1  - Kunz, Wolfgang
T1  - Implication-based gate-level synthesis for low-power
Y1  - 1996
SN  - 0-7803-3571-6
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Reddy, S. M.
A1  - Subodh, M.
A1  - Pradhan, D. K.
T1  - Efficient logic verification in a synthesis environment
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Logic equivalence checking by optimization techniues
Y1  - 1996
ER  -