TY  - JOUR
A1  - Gerber, Stefan
A1  - Gössel, Michael
T1  - Detection of permanent faults of a floating point adder by pseudoduplication
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Bogue, Ted
A1  - Jürgensen, Helmut
A1  - Gössel, Michael
T1  - Design of cover circuits for monitoring the output of a MISR
Y1  - 1994
SN  - 0-8186-6307-3 , 0-8186-6306-5
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Morosov, Andrej
A1  - Saposhnikov, V. V.
A1  - Saposhnikov, VL. V.
T1  - Design of combinational self-testing devices with unidirectionally independent outputs
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Richter, Peter
T1  - Efficient shortest path algorithms for road traffic optimization
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Schröder-Preikschat, Wolfgang
T1  - PEACE - software backplane for parallel computing
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Sommerfeld, Erdmute
T1  - Operations on cognitive structures : their modelling on the basis of graph theory
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Pradhan, D. K.
T1  - Recursive learning : a new implication technique for efficient solutions to CAD problems : test, verification and optimization
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Tarnick, Steffen
T1  - Bounding error masking in linear output space compression schemes
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Tarnick, Steffen
T1  - Controllable self-checking checkers for conditional concurrent checking
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Böhlau, Peter
T1  - Zero aliasing compression based on groups of weakly independent outputs in circuits with high complexity for two fault models
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Menon, P.
T1  - Multi-level logic optimization by implication analysis
Y1  - 1994
SN  - 0-89791-690-5
SN  - 0-8186-6416-9
SN  - 0-8186-6417-7
ER  - 
TY  - JOUR
A1  - Cobernuss, M.
T1  - Bused interconnection network for parallel memory with linear storage
Y1  - 1994
SN  - 3-05-501602-5
ER  -