TY  - JOUR
A1  - Dug, Mehmed
A1  - Weidling, Stefan
A1  - Sogomonyan, Egor
A1  - Jokic, Dejan
A1  - Krstić, Miloš
T1  - Full error detection and correction method applied on pipelined structure using two approaches
JF  - Journal of circuits, systems and computers
N2  - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.
KW  - Fault tolerance
KW  - FEDC
KW  - EDC
Y1  - 2020
U6  - https://doi.org/10.1142/S0218126620502187
SN  - 0218-1266
SN  - 1793-6454
VL  - 29
IS  - 13
PB  - World Scientific
CY  - Singapore
ER  -