TY  - JOUR
A1  - Kuentzer, Felipe A.
A1  - Krstić, Miloš
T1  - Soft error detection and correction architecture for asynchronous bundled data designs
JF  - IEEE transactions on circuits and systems
N2  - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%.
KW  - circuit Faults
KW  - latches
KW  - Fault tolerance
KW  - Fault tolerant systems
KW  - timing
KW  - clocks
KW  - transient analysis
KW  - asynchrounous design
KW  - soft errors
KW  - transient Faults
KW  - bundled data
KW  - click controller
KW  - self-checking
KW  - concurrent checking
KW  - DMR
KW  - TMR
Y1  - 2020
U6  - https://doi.org/10.1109/TCSI.2020.2998911
SN  - 1549-8328
SN  - 1558-0806
VL  - 67
IS  - 12
SP  - 4883
EP  - 4894
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  - 
TY  - JOUR
A1  - Dug, Mehmed
A1  - Weidling, Stefan
A1  - Sogomonyan, Egor
A1  - Jokic, Dejan
A1  - Krstić, Miloš
T1  - Full error detection and correction method applied on pipelined structure using two approaches
JF  - Journal of circuits, systems and computers
N2  - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.
KW  - Fault tolerance
KW  - FEDC
KW  - EDC
Y1  - 2020
U6  - https://doi.org/10.1142/S0218126620502187
SN  - 0218-1266
SN  - 1793-6454
VL  - 29
IS  - 13
PB  - World Scientific
CY  - Singapore
ER  -