TY  - BOOK
A1  - Marienfeld, Daniel
A1  - Sogomonyan, Egor S.
A1  - Ocheretnij, V.
A1  - Gössel, Michael
T1  - Self-checking Output-duplicated Booth-2 Multiplier
T3  - Preprint / Universität Potsdam, Institut für Informatik
Y1  - 2005
SN  - 0946-7580
VL  - 2005, 1
PB  - Univ.
CY  - Potsdam
ER  - 
TY  - BOOK
A1  - Sogomonyan, Egor S.
A1  - Marienfeld, Daniel
A1  - Gössel, Michael
T1  - Fehlerkorrektur und Fehlererkennung
T3  - Preprint / Universität Potsdam, Institut für Informatik
Y1  - 2006
SN  - 0946-7580
VL  - 2006, 3
PB  - Univ.
CY  - Potsdam
ER  - 
TY  - JOUR
A1  - Ocheretnij, Vitalij
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
A1  - Marienfeld, Daniel
T1  - Modulo p=3 checking for a carry select adder
N2  - In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks
Y1  - 2006
UR  - http://www.springerlink.com/content/100286
U6  - https://doi.org/10.1007/s10836-006-6260-8
ER  - 
TY  - JOUR
A1  - Singh, Adit D.
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
A1  - Seuring, Markus
T1  - Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - New totally self-checking ripple and carry look-ahead adders
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Seuring, Markus
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben für online-Fehlererkennungen und Selbstests
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
A1  - Morosov, Andrej
T1  - A new totally error propagating compactor for arbitrary cores with digital interfaces
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - On-line Test auf der Grundlage eines die Parität erhaltenden Signaturanalysators
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Hlawiczka, A.
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A linear code-preserving signature analyzer COPMISR
Y1  - 1997
SN  - 0-8186-7810-0
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Singh, Adit D.
A1  - Gössel, Michael
T1  - A multi-mode scannable memory element for high test application efficiency and delay testing
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Seuring, Markus
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A structural approach for space compaction for concurrent checking and BIST
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Singh, Adit D.
A1  - Gössel, Michael
T1  - A scan based concrrent BIST approach for low cost on-line testing
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Hartje, Hendrik
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Synthesis of code-disjoint combinational circuits
Y1  - 1997
ER  - 
TY  - BOOK
A1  - Seuring, Markus
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A structural approach for space compaction for concurrent checking and BIST
T3  - Preprint / Universität Potsdam, Institut für Informatik
Y1  - 1997
SN  - 0946-7580
VL  - 1997, 01
PB  - Univ. Potsdam
CY  - Potsdam [u.a.]
ER  - 
TY  - JOUR
A1  - Hartje, Hendrik
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
T1  - Code disjoint circuits for partity codes
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A new self-testing parity checker for ultra-reliable applications
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
T1  - Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
T1  - A new parity preserving multi-input signature analyser
Y1  - 1995
ER  - 
TY  - JOUR
A1  - Kundu, S.
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
A1  - Tarnick, Steffen
T1  - Self-checking comparator with one periodiv output
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design
Y1  - 1994
ER  - 
TY  - BOOK
A1  - Goessel, Michael
A1  - Ocheretny, Vitaly
A1  - Sogomonyan, Egor S.
A1  - Marienfeld, Daniel
T1  - New methods of concurrent checking
T3  - Frontiers in electronic testing
Y1  - 2008
SN  - 978-1-402-08419-5
U6  - https://doi.org/10.1007/978-1-4020-8420-1
VL  - 42
PB  - Springer
CY  - Dordrecht; Heidelberg
ER  - 
TY  - BOOK
A1  - Sogomonyan, Egor S.
A1  - Marienfeld, Daniel
A1  - Ocheretnij, V.
A1  - Gössel, Michael
T1  - A new self-checking sum-bit duplicated carry-select adder
T3  - Preprint / Universität Potsdam, Institut für Informatik
Y1  - 2003
SN  - 0946-7580
VL  - 2003, 5
PB  - Univ.
CY  - Potsdam
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Singh, Adit D.
A1  - Gössel, Michael
T1  - A multi-mode scannable memory element for high test application efficiency and delay testing
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Krstić, Miloš
A1  - Weidling, Stefan
A1  - Petrovic, Vladimir
A1  - Sogomonyan, Egor S.
T1  - Enhanced architectures for soft error detection and correction in combinational and sequential circuits
JF  - Microelectronics Reliability
N2  - In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.
Y1  - 2016
SN  - 0026-2714
VL  - 56
SP  - 212
EP  - 220
ER  -