TY  - JOUR
A1  - Breitenreiter, Anselm
A1  - Andjelković, Marko
A1  - Schrape, Oliver
A1  - Krstić, Miloš
T1  - Fast error propagation probability estimates by answer set programming and approximate model counting
JF  - IEEE Access
N2  - We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1%.
KW  - Circuit faults
KW  - Integrated circuit modeling
KW  - Programming
KW  - Analytical models
KW  - Search problems
KW  - Flip-flops
KW  - Encoding
KW  - Answer set programming
KW  - approximate model counting
KW  - error propagation
KW  - radhard design
KW  - reliability analysis
KW  - selective fault tolerance
KW  - single event upsets
Y1  - 2022
U6  - https://doi.org/10.1109/ACCESS.2022.3174564
SN  - 2169-3536
VL  - 10
SP  - 51814
EP  - 51825
PB  - Inst. of Electr. and Electronics Engineers
CY  - Piscataway
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Breitenreiter, Anselm
A1  - Andjelkovic, Marko
A1  - Chen, Junchao
A1  - Babic, Milan
A1  - Krstić, Miloš
T1  - Double cell upsets mitigation through triple modular redundancy
JF  - Microelectronics Journal
N2  - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.
KW  - Triple modular redundancy (TMR)
KW  - Double cell upsets (DCUs)
Y1  - 2019
U6  - https://doi.org/10.1016/j.mejo.2019.104683
SN  - 0026-2692
SN  - 1879-2391
VL  - 96
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Schrape, Oliver
A1  - Andjelkovic, Marko
A1  - Breitenreiter, Anselm
A1  - Zeidler, Steffen
A1  - Balashov, Alexey
A1  - Krstić, Miloš
T1  - Design and evaluation of radiation-hardened standard cell flip-flops
JF  - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers
N2  - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.
KW  - Single event effect
KW  - fault tolerance
KW  - triple modular redundancy
KW  - ASIC
KW  - design flow
KW  - radhard design
Y1  - 2021
U6  - https://doi.org/10.1109/TCSI.2021.3109080
SN  - 1549-8328
SN  - 1558-0806
SN  - 1057-7122
VL  - 68
IS  - 11
SP  - 4796
EP  - 4809
PB  - Inst. of Electr. and Electronics Engineers
CY  - New York, NY
ER  -