TY - JOUR A1 - Saposhnikov, V. V. A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - A new design method for self-checking unidirectional combinational circuits Y1 - 1998 ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A structural approach for space compaction for concurrent checking and BIST Y1 - 1998 ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - A new parity preserving multi-input signature analyser Y1 - 1995 ER - TY - JOUR A1 - Saposhnikov, Va. V. A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Design of self-checking unidirectional combinational circuits with low area overhead Y1 - 1996 ER - TY - BOOK A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Morozov, Alexei A1 - Gössel, Michael T1 - Necessary and Sufficient Conditions for the Existence of Self-Checking Circuits ba Use of Complementary Circuits T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2004 SN - 0946-7580 VL - 2004, 1 PB - Univ. CY - Potsdam ER - TY - THES A1 - Andjelkovic, Marko T1 - A methodology for characterization, modeling and mitigation of single event transient effects in CMOS standard combinational cells T1 - Eine Methode zur Charakterisierung, Modellierung und Minderung von SET Effekten in kombinierten CMOS-Standardzellen N2 - With the downscaling of CMOS technologies, the radiation-induced Single Event Transient (SET) effects in combinational logic have become a critical reliability issue for modern integrated circuits (ICs) intended for operation under harsh radiation conditions. The SET pulses generated in combinational logic may propagate through the circuit and eventually result in soft errors. It has thus become an imperative to address the SET effects in the early phases of the radiation-hard IC design. In general, the soft error mitigation solutions should accommodate both static and dynamic measures to ensure the optimal utilization of available resources. An efficient soft-error-aware design should address synergistically three main aspects: (i) characterization and modeling of soft errors, (ii) multi-level soft error mitigation, and (iii) online soft error monitoring. Although significant results have been achieved, the effectiveness of SET characterization methods, accuracy of predictive SET models, and efficiency of SET mitigation measures are still critical issues. Therefore, this work addresses the following topics: (i) Characterization and modeling of SET effects in standard combinational cells, (ii) Static mitigation of SET effects in standard combinational cells, and (iii) Online particle detection, as a support for dynamic soft error mitigation. Since the standard digital libraries are widely used in the design of radiation-hard ICs, the characterization of SET effects in standard cells and the availability of accurate SET models for the Soft Error Rate (SER) evaluation are the main prerequisites for efficient radiation-hard design. This work introduces an approach for the SPICE-based standard cell characterization with the reduced number of simulations, improved SET models and optimized SET sensitivity database. It has been shown that the inherent similarities in the SET response of logic cells for different input levels can be utilized to reduce the number of required simulations. Based on characterization results, the fitting models for the SET sensitivity metrics (critical charge, generated SET pulse width and propagated SET pulse width) have been developed. The proposed models are based on the principle of superposition, and they express explicitly the dependence of the SET sensitivity of individual combinational cells on design, operating and irradiation parameters. In contrast to the state-of-the-art characterization methodologies which employ extensive look-up tables (LUTs) for storing the simulation results, this work proposes the use of LUTs for storing the fitting coefficients of the SET sensitivity models derived from the characterization results. In that way the amount of characterization data in the SET sensitivity database is reduced significantly. The initial step in enhancing the robustness of combinational logic is the application of gate-level mitigation techniques. As a result, significant improvement of the overall SER can be achieved with minimum area, delay and power overheads. For the SET mitigation in standard cells, it is essential to employ the techniques that do not require modifying the cell structure. This work introduces the use of decoupling cells for improving the robustness of standard combinational cells. By insertion of two decoupling cells at the output of a target cell, the critical charge of the cell’s output node is increased and the attenuation of short SETs is enhanced. In comparison to the most common gate-level techniques (gate upsizing and gate duplication), the proposed approach provides better SET filtering. However, as there is no single gate-level mitigation technique with optimal performance, a combination of multiple techniques is required. This work introduces a comprehensive characterization of gate-level mitigation techniques aimed to quantify their impact on the SET robustness improvement, as well as introduced area, delay and power overhead per gate. By characterizing the gate-level mitigation techniques together with the standard cells, the required effort in subsequent SER analysis of a target design can be reduced. The characterization database of the hardened standard cells can be utilized as a guideline for selection of the most appropriate mitigation solution for a given design. As a support for dynamic soft error mitigation techniques, it is important to enable the online detection of energetic particles causing the soft errors. This allows activating the power-greedy fault-tolerant configurations based on N-modular redundancy only at the high radiation levels. To enable such a functionality, it is necessary to monitor both the particle flux and the variation of particle LET, as these two parameters contribute significantly to the system SER. In this work, a particle detection approach based on custom-sized pulse stretching inverters is proposed. Employing the pulse stretching inverters connected in parallel enables to measure the particle flux in terms of the number of detected SETs, while the particle LET variations can be estimated from the distribution of SET pulse widths. This approach requires a purely digital processing logic, in contrast to the standard detectors which require complex mixed-signal processing. Besides the possibility of LET monitoring, additional advantages of the proposed particle detector are low detection latency and power consumption, and immunity to error accumulation. The results achieved in this thesis can serve as a basis for establishment of an overall soft-error-aware database for a given digital library, and a comprehensive multi-level radiation-hard design flow that can be implemented with the standard IC design tools. The following step will be to evaluate the achieved results with the irradiation experiments. N2 - Mit der Verkleinerung der Strukturen moderner CMOS-Technologien sind strahlungsinduzierte Single Event Transient (SET)-Effekte in kombinatorischer Logik zu einem kritischen Zuverlässigkeitsproblem in integrierten Schaltkreisen (ICs) geworden, die für den Betrieb unter rauen Strahlungsbedingungen (z. B. im Weltraum) vorgesehen sind. Die in der Kombinationslogik erzeugten SET-Impulse können durch die Schaltungen propagieren und schließlich in Speicherelementen (z.B. Flip-Flops oder Latches) zwischengespeichert werden, was zu sogenannten Soft-Errors und folglich zu Datenbeschädigungen oder einem Systemausfall führt. Daher ist es in den frühen Phasen des strahlungsharten IC-Designs unerlässlich geworden, die SET-Effekte systematisch anzugehen. Im Allgemeinen sollten die Lösungen zur Minderung von Soft-Errors sowohl statische als auch dynamische Maßnahmen berücksichtigen, um die optimale Nutzung der verfügbaren Ressourcen sicherzustellen. Somit sollte ein effizientes Soft-Error-Aware-Design drei Hauptaspekte synergistisch berücksichtigen: (i) die Charakterisierung und Modellierung von Soft-Errors, (ii) eine mehrstufige-Soft-Error-Minderung und (iii) eine Online-Soft-Error-Überwachung. Obwohl signifikante Ergebnisse erzielt wurden, sind die Wirksamkeit der SET-Charakterisierung, die Genauigkeit von Vorhersagemodellen und die Effizienz der Minderungsmaßnahmen immer noch die kritischen Punkte. Daher stellt diese Arbeit die folgenden Originalbeiträge vor: • Eine ganzheitliche Methodik zur SPICE-basierten Charakterisierung von SET-Effekten in kombinatorischen Standardzellen und entsprechenden Härtungskonfigurationen auf Gate-Ebene mit reduzierter Anzahl von Simulationen und reduzierter SET-Sensitivitätsdatenbank. • Analytische Modelle für SET-Empfindlichkeit (kritische Ladung, erzeugte SET-Pulsbreite und propagierte SET-Pulsbreite), basierend auf dem Superpositionsprinzip und Anpassung der Ergebnisse aus SPICE-Simulationen. • Ein Ansatz zur SET-Abschwächung auf Gate-Ebene, der auf dem Einfügen von zwei Entkopplungszellen am Ausgang eines Logikgatters basiert, was den Anstieg der kritischen Ladung und die signifikante Unterdrückung kurzer SETs beweist. • Eine vergleichende Charakterisierung der vorgeschlagenen SET-Abschwächungstechnik mit Entkopplungszellen und sieben bestehenden Techniken durch eine quantitative Bewertung ihrer Auswirkungen auf die Verbesserung der SET-Robustheit einzelner Logikgatter. • Ein Partikeldetektor auf Basis von Impulsdehnungs-Invertern in Skew-Größe zur Online-Überwachung des Partikelflusses und der LET-Variationen mit rein digitaler Anzeige. Die in dieser Dissertation erzielten Ergebnisse können als Grundlage für den Aufbau einer umfassenden Soft-Error-aware-Datenbank für eine gegebene digitale Bibliothek und eines umfassenden mehrstufigen strahlungsharten Designflusses dienen, der mit den Standard-IC-Designtools implementiert werden kann. Im nächsten Schritt werden die mit den Bestrahlungsexperimenten erzielten Ergebnisse ausgewertet. KW - Single Event Transient KW - radiation hardness design KW - Single Event Transient KW - Strahlungshärte Entwurf Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:517-opus4-534843 ER - TY - JOUR A1 - Schrape, Oliver A1 - Andjelkovic, Marko A1 - Breitenreiter, Anselm A1 - Zeidler, Steffen A1 - Balashov, Alexey A1 - Krstić, Miloš T1 - Design and evaluation of radiation-hardened standard cell flip-flops JF - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers N2 - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant. KW - Single event effect KW - fault tolerance KW - triple modular redundancy KW - ASIC KW - design flow KW - radhard design Y1 - 2021 U6 - https://doi.org/10.1109/TCSI.2021.3109080 SN - 1549-8328 SN - 1558-0806 SN - 1057-7122 VL - 68 IS - 11 SP - 4796 EP - 4809 PB - Inst. of Electr. and Electronics Engineers CY - New York, NY ER - TY - JOUR A1 - Breitenreiter, Anselm A1 - Andjelković, Marko A1 - Schrape, Oliver A1 - Krstić, Miloš T1 - Fast error propagation probability estimates by answer set programming and approximate model counting JF - IEEE Access N2 - We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1%. KW - Circuit faults KW - Integrated circuit modeling KW - Programming KW - Analytical models KW - Search problems KW - Flip-flops KW - Encoding KW - Answer set programming KW - approximate model counting KW - error propagation KW - radhard design KW - reliability analysis KW - selective fault tolerance KW - single event upsets Y1 - 2022 U6 - https://doi.org/10.1109/ACCESS.2022.3174564 SN - 2169-3536 VL - 10 SP - 51814 EP - 51825 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST Y1 - 1996 ER - TY - JOUR A1 - Li, Yuanqing A1 - Chen, Li A1 - Nofal, Issam A1 - Chen, Mo A1 - Wang, Haibin A1 - Liu, Rui A1 - Chen, Qingyu A1 - Krstić, Miloš A1 - Shi, Shuting A1 - Guo, Gang A1 - Baeg, Sang H. A1 - Wen, Shi-Jie A1 - Wong, Richard T1 - Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree JF - Microelectronics reliability N2 - The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. KW - Clock tree KW - Modeling KW - Single-event transient (SET) Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2018.05.016 SN - 0026-2714 VL - 87 SP - 24 EP - 32 PB - Elsevier CY - Oxford ER - TY - JOUR A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Design of self dual fault-secure combinational circuits Y1 - 1997 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Dimitriev, Alexej A1 - Gössel, Michael T1 - Self-dual duplication for error detection Y1 - 1998 ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael T1 - A structural approach for space compaction for sequential circuits Y1 - 1999 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Synthesis of code-disjoint combinational circuits Y1 - 1997 ER - TY - THES A1 - Weidling, Stefan T1 - Neue Ansätze zur Verbesserung der Fehlertoleranz gegenüber transienten Fehlern in sequentiellen Schaltungen Y1 - 2016 ER - TY - GEN A1 - Krstić, Miloš A1 - Jentzsch, Anne-Kristin T1 - Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach T2 - 2018 12TH European Workshop on Microelectronics Education (EWME) N2 - This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated. KW - reliability KW - safety KW - security KW - automated driving KW - joint lab Y1 - 2018 SN - 978-1-5386-1157-9 SP - 21 EP - 22 PB - IEEE CY - New York ER - TY - JOUR A1 - Singh, Adit D. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Seuring, Markus T1 - Testability evaluation of sequential designs incorporating the multi-mode scannable memory element Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael A1 - Morosov, Andrej T1 - A method of construction of combinational self-checking units with detection of all single faults Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Morosov, Andrej T1 - A new totally error propagating compactor for arbitrary cores with digital interfaces Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Morosov, Andrej A1 - Saposhnikov, V. V. A1 - Saposhnikov, VL. V. T1 - Design of combinational self-testing devices with unidirectionally independent outputs Y1 - 1994 ER - TY - BOOK A1 - Marienfeld, Daniel A1 - Sogomonyan, Egor S. A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - Self-checking Output-duplicated Booth-2 Multiplier T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2005 SN - 0946-7580 VL - 2005, 1 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A scan based concrrent BIST approach for low cost on-line testing Y1 - 1998 ER - TY - BOOK A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel A1 - Gössel, Michael T1 - Fehlerkorrektur und Fehlererkennung T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2006 SN - 0946-7580 VL - 2006, 3 PB - Univ. CY - Potsdam ER - TY - THES A1 - Nieß, Günther T1 - Modellierung und Erkennung von technischen Fehlern mittels linearer und nichtlinearer Codes Y1 - 2016 ER - TY - BOOK A1 - Börner, Ferdinand A1 - Gössel, Michael T1 - Grundlagen digitaler Systeme Y1 - 2005 SN - 978-3-937786-46-9 PB - Univ.-Verl. CY - Potsdam ER - TY - JOUR A1 - Dmitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Self-dual sequential circuits for concurrent chechking Y1 - 1999 SN - 0-7695-0390-X ; 0-7695-0391-8 ER - TY - BOOK A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - A new self-checking sum-bit duplicated carry-select adder T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2003 SN - 0946-7580 VL - 2003, 5 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A multi-mode scannable memory element for high test application efficiency and delay testing Y1 - 1999 ER - TY - BOOK A1 - Wu, K. A1 - Karri, R. A1 - Kuznetsov, Grigory A1 - Gössel, Michael T1 - Low Cost Concurrent Error Detection for the Advanced Encryption Standart T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2003 SN - 0946-7580 VL - 2003, 8 PB - Univ. CY - Potsdam ER - TY - BOOK A1 - Börner, Ferdinand A1 - Gössel, Michael ED - Gössel, Michael T1 - Grundlagen digitaler Systeme Y1 - 2001 SN - 3-935024-34-7 SN - 978-3-935024-34-1 PB - Univ.-Bibliothek Publ.-Stelle CY - Potsdam ER - TY - BOOK A1 - Sapoznikov, V. V. A1 - Sapoznikov, VL. V. A1 - Gössel, Michael T1 - Samodvojstvennye diskretnye ustrojstva Y1 - 2001 SN - 5-283-04748-2 PB - ?nergoatomizdat CY - Sankt-Peterburg ER - TY - BOOK A1 - Börner, Ferdinand A1 - Gössel, Michael T1 - Grundlagen digitaler Systeme Y1 - 2000 SN - 3-9806494-9-0 PB - Univ.-Bibliothek Publ.-Stelle CY - Potsdam ER - TY - JOUR A1 - Ocheretnij, Vitalij A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel T1 - Modulo p=3 checking for a carry select adder N2 - In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks Y1 - 2006 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-006-6260-8 ER - TY - JOUR A1 - Otscheretnij, Vitalij A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Fault-tolerant self-dual circuits Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, Vl. V. V. V. A1 - Moshanin, Vl. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Experimental results for self-dual multi-output combinational circuits Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Dimitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. T1 - Eine selbsttestende Struktur zur on-line Fehlererkennung in kombinatorischen Schaltungen Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Ocheretnij, V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Modified TMR-system with reduced hardware overhead Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - New totally self-checking ripple and carry look-ahead adders Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael T1 - A new method of redundancy addition for circuit optimization JF - Preprint / Universität Potsdam, Institut für Informatik Y1 - 1999 SN - 0946-7580 VL - 1999, 08 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - Design of cover circuits for monitoring the output of a MISR Y1 - 1994 SN - 0-8186-6307-3 , 0-8186-6306-5 ER - TY - JOUR A1 - Morosov, Andrej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung Y1 - 1997 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Dimitriev, Alexej A1 - Gössel, Michael A1 - Saposhnikov, Va. V. T1 - Self-dual parity checking - a new method for on-line testing Y1 - 1996 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Kundu, S. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Tarnick, Steffen T1 - Self-checking comparator with one periodiv output Y1 - 1996 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - Code disjoint circuits for partity codes Y1 - 1997 ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - BIST with negligible aliasing through random cover circuits Y1 - 1995 ER - TY - JOUR A1 - Rabenalt, Thomas A1 - Richter, Michael A1 - Pöhl, Frank A1 - Gössel, Michael T1 - Highly efficient test response compaction using a hierarchical x-masking technique JF - IEEE transactions on computer-aided design of integrated circuits and systems N2 - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x. KW - Design for testability (DFT) KW - test response compaction KW - X-masking KW - X-values Y1 - 2012 U6 - https://doi.org/10.1109/TCAD.2011.2181847 SN - 0278-0070 VL - 31 IS - 6 SP - 950 EP - 957 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER - TY - JOUR A1 - Dug, Mehmed A1 - Weidling, Stefan A1 - Sogomonyan, Egor A1 - Jokic, Dejan A1 - Krstić, Miloš T1 - Full error detection and correction method applied on pipelined structure using two approaches JF - Journal of circuits, systems and computers N2 - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach. KW - Fault tolerance KW - FEDC KW - EDC Y1 - 2020 U6 - https://doi.org/10.1142/S0218126620502187 SN - 0218-1266 SN - 1793-6454 VL - 29 IS - 13 PB - World Scientific CY - Singapore ER - TY - JOUR A1 - Li, Yuanqing A1 - Breitenreiter, Anselm A1 - Andjelkovic, Marko A1 - Chen, Junchao A1 - Babic, Milan A1 - Krstić, Miloš T1 - Double cell upsets mitigation through triple modular redundancy JF - Microelectronics Journal N2 - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit. KW - Triple modular redundancy (TMR) KW - Double cell upsets (DCUs) Y1 - 2019 U6 - https://doi.org/10.1016/j.mejo.2019.104683 SN - 0026-2692 SN - 1879-2391 VL - 96 PB - Elsevier CY - Oxford ER -