TY - JOUR A1 - Michallek, Florian A1 - Genske, Ulrich A1 - Niehues, Stefan Markus A1 - Hamm, Bernd A1 - Jahnke, Paul T1 - Deep learning reconstruction improves radiomics feature stability and discriminative power in abdominal CT imaging BT - a phantom study JF - European Radiology N2 - Objectives To compare image quality of deep learning reconstruction (AiCE) for radiomics feature extraction with filtered back projection (FBP), hybrid iterative reconstruction (AIDR 3D), and model-based iterative reconstruction (FIRST). Methods Effects of image reconstruction on radiomics features were investigated using a phantom that realistically mimicked a 65-year-old patient's abdomen with hepatic metastases. The phantom was scanned at 18 doses from 0.2 to 4 mGy, with 20 repeated scans per dose. Images were reconstructed with FBP, AIDR 3D, FIRST, and AiCE. Ninety-three radiomics features were extracted from 24 regions of interest, which were evenly distributed across three tissue classes: normal liver, metastatic core, and metastatic rim. Features were analyzed in terms of their consistent characterization of tissues within the same image (intraclass correlation coefficient >= 0.75), discriminative power (Kruskal-Wallis test p value < 0.05), and repeatability (overall concordance correlation coefficient >= 0.75). Results The median fraction of consistent features across all doses was 6%, 8%, 6%, and 22% with FBP, AIDR 3D, FIRST, and AiCE, respectively. Adequate discriminative power was achieved by 48%, 82%, 84%, and 92% of features, and 52%, 20%, 17%, and 39% of features were repeatable, respectively. Only 5% of features combined consistency, discriminative power, and repeatability with FBP, AIDR 3D, and FIRST versus 13% with AiCE at doses above 1 mGy and 17% at doses >= 3 mGy. AiCE was the only reconstruction technique that enabled extraction of higher-order features. Conclusions AiCE more than doubled the yield of radiomics features at doses typically used clinically. Inconsistent tissue characterization within CT images contributes significantly to the poor stability of radiomics features. KW - Tomography KW - X-ray computed KW - Phantoms KW - imaging KW - Liver neoplasms KW - Algorithms KW - Reproducibility of results Y1 - 2022 U6 - https://doi.org/10.1007/s00330-022-08592-y SN - 1432-1084 VL - 32 IS - 7 SP - 4587 EP - 4595 PB - Springer CY - New York ER - TY - JOUR A1 - Dines, Nicoleta A1 - Liu, Xiaochun A1 - Schulze, Bert-Wolfgang T1 - Edge quantisation of elliptic operators JF - Preprint / Universität Potsdam, Institut für Mathematik, Arbeitsgruppe Partiell N2 - The ellipticity of operators on a manifold with edge is defined as the bijectivity of the components of a principal symbolic hierarchy sigma = (sigma(psi), sigma(boolean AND)), where the second component takes values in operators on the infinite model cone of the local wedges. In the general understanding of edge problems there are two basic aspects: Quantisation of edge-degenerate operators in weighted Sobolev spaces, and verifying the ellipticity of the principal edge symbol sigma(boolean AND) which includes the (in general not explicity known) number of additional conditions of trace and potential type on the edge. We focus here on these questions and give explicit answers for a wide class of elliptic operators that are connected with the ellipticity of edge boundary value problems and reductions to the boundary. In particular, we study the edge quantisation and ellipticity for Dirichlet-Neumann operators with respect to interfaces of some codimension on a boundary. We show analogues of the Agranovich-Dynin formula for edge boundary value problems. Y1 - 2009 UR - http://www.springerlink.com/content/103082 U6 - https://doi.org/10.1007/s00605-008-0058-y SN - 1437-739X ER - TY - JOUR A1 - Bandyopadhyay, Soumyadip A1 - Sarkar, Dipankar A1 - Mandal, Chittaranjan A1 - Giese, Holger T1 - Translation validation of coloured Petri net models of programs on integers JF - Acta informatica N2 - Programs are often subjected to significant optimizing and parallelizing transformations based on extensive dependence analysis. Formal validation of such transformations needs modelling paradigms which can capture both control and data dependences in the program vividly. Being value-based with an inherent scope of capturing parallelism, the untimed coloured Petri net (CPN) models, reported in the literature, fit the bill well; accordingly, they are likely to be more convenient as the intermediate representations (IRs) of both the source and the transformed codes for translation validation than strictly sequential variable-based IRs like sequential control flow graphs (CFGs). In this work, an efficient path-based equivalence checking method for CPN models of programs on integers is presented. Extensive experimentation has been carried out on several sequential and parallel examples. Complexity and correctness issues have been treated rigorously for the method. Y1 - 2022 U6 - https://doi.org/10.1007/s00236-022-00419-z SN - 0001-5903 SN - 1432-0525 VL - 59 IS - 6 SP - 725 EP - 759 PB - Springer CY - New York ER - TY - JOUR A1 - Omranian, Nooshin A1 - Müller-Röber, Bernd A1 - Nikoloski, Zoran T1 - Segmentation of biological multivariate time-series data JF - Scientific reports N2 - Time-series data from multicomponent systems capture the dynamics of the ongoing processes and reflect the interactions between the components. The progression of processes in such systems usually involves check-points and events at which the relationships between the components are altered in response to stimuli. Detecting these events together with the implicated components can help understand the temporal aspects of complex biological systems. Here we propose a regularized regression-based approach for identifying breakpoints and corresponding segments from multivariate time-series data. In combination with techniques from clustering, the approach also allows estimating the significance of the determined breakpoints as well as the key components implicated in the emergence of the breakpoints. Comparative analysis with the existing alternatives demonstrates the power of the approach to identify biologically meaningful breakpoints in diverse time-resolved transcriptomics data sets from the yeast Saccharomyces cerevisiae and the diatom Thalassiosira pseudonana. Y1 - 2015 U6 - https://doi.org/10.1038/srep08937 SN - 2045-2322 VL - 5 PB - Nature Publ. Group CY - London ER - TY - JOUR A1 - Chen, Junchao A1 - Lange, Thomas A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Lu, Li A1 - Krstić, Miloš T1 - Solar particle event and single event upset prediction from SRAM-based monitor and supervised machine learning JF - IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers N2 - The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels. KW - Machine learning KW - Single event upsets KW - Random access memory KW - monitoring KW - machine learning algorithms KW - predictive models KW - space missions KW - solar particle event KW - single event upset KW - machine learning KW - online learning KW - hardware accelerator KW - reliability KW - self-adaptive multiprocessing system Y1 - 2022 U6 - https://doi.org/10.1109/TETC.2022.3147376 SN - 2168-6750 VL - 10 IS - 2 SP - 564 EP - 580 PB - Institute of Electrical and Electronics Engineers CY - [New York, NY] ER - TY - JOUR A1 - Andjelković, Marko A1 - Chen, Junchao A1 - Simevski, Aleksandar A1 - Schrape, Oliver A1 - Krstić, Miloš A1 - Kraemer, Rolf T1 - Monitoring of particle count rate and LET variations with pulse stretching inverters JF - IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society N2 - This study investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and linear energy transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inverters, and the required sensing area is obtained by connecting up to 12 two-inverter cells in parallel and employing the required number of parallel arrays. The incident particles are detected as single-event transients (SETs), whereby the SET count rate denotes the particle count rate, while the SET pulsewidth distribution depicts the LET variations. The advantage of the proposed solution is the possibility to sense the LET variations using fully digital processing logic. SPICE simulations conducted on IHP's 130-nm CMOS technology have shown that the SET pulsewidth varies by approximately 550 ps over the LET range from 1 to 100 MeV center dot cm(2) center dot mg(-1). The proposed detector is intended for triggering the fault-tolerant mechanisms within a self-adaptive multiprocessing system employed in space. It can be implemented as a standalone detector or integrated in the same chip with the target system. KW - Particle detector KW - pulse stretching inverters KW - single-event transient KW - (SET) count rate KW - SET pulsewidth distribution Y1 - 2021 U6 - https://doi.org/10.1109/TNS.2021.3076400 SN - 0018-9499 SN - 1558-1578 VL - 68 IS - 8 SP - 1772 EP - 1781 PB - Institute of Electrical and Electronics Engineers CY - New York, NY ER - TY - JOUR A1 - Dimitriev, Alexej A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael A1 - Saposhnikov, V. V. T1 - On-line testing by self-dual duplication Y1 - 1997 ER - TY - JOUR A1 - Saposhnikov, V. V. A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - A new design method for self-checking unidirectional combinational circuits Y1 - 1998 ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A structural approach for space compaction for concurrent checking and BIST Y1 - 1998 ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - A new parity preserving multi-input signature analyser Y1 - 1995 ER - TY - JOUR A1 - Saposhnikov, Va. V. A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Design of self-checking unidirectional combinational circuits with low area overhead Y1 - 1996 ER - TY - JOUR A1 - Schrape, Oliver A1 - Andjelkovic, Marko A1 - Breitenreiter, Anselm A1 - Zeidler, Steffen A1 - Balashov, Alexey A1 - Krstić, Miloš T1 - Design and evaluation of radiation-hardened standard cell flip-flops JF - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers N2 - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant. KW - Single event effect KW - fault tolerance KW - triple modular redundancy KW - ASIC KW - design flow KW - radhard design Y1 - 2021 U6 - https://doi.org/10.1109/TCSI.2021.3109080 SN - 1549-8328 SN - 1558-0806 SN - 1057-7122 VL - 68 IS - 11 SP - 4796 EP - 4809 PB - Inst. of Electr. and Electronics Engineers CY - New York, NY ER - TY - JOUR A1 - Breitenreiter, Anselm A1 - Andjelković, Marko A1 - Schrape, Oliver A1 - Krstić, Miloš T1 - Fast error propagation probability estimates by answer set programming and approximate model counting JF - IEEE Access N2 - We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1%. KW - Circuit faults KW - Integrated circuit modeling KW - Programming KW - Analytical models KW - Search problems KW - Flip-flops KW - Encoding KW - Answer set programming KW - approximate model counting KW - error propagation KW - radhard design KW - reliability analysis KW - selective fault tolerance KW - single event upsets Y1 - 2022 U6 - https://doi.org/10.1109/ACCESS.2022.3174564 SN - 2169-3536 VL - 10 SP - 51814 EP - 51825 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST Y1 - 1996 ER - TY - JOUR A1 - Li, Yuanqing A1 - Chen, Li A1 - Nofal, Issam A1 - Chen, Mo A1 - Wang, Haibin A1 - Liu, Rui A1 - Chen, Qingyu A1 - Krstić, Miloš A1 - Shi, Shuting A1 - Guo, Gang A1 - Baeg, Sang H. A1 - Wen, Shi-Jie A1 - Wong, Richard T1 - Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree JF - Microelectronics reliability N2 - The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method. KW - Clock tree KW - Modeling KW - Single-event transient (SET) Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2018.05.016 SN - 0026-2714 VL - 87 SP - 24 EP - 32 PB - Elsevier CY - Oxford ER - TY - JOUR A1 - Morosov, Andrej A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Design of self dual fault-secure combinational circuits Y1 - 1997 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Dimitriev, Alexej A1 - Gössel, Michael T1 - Self-dual duplication for error detection Y1 - 1998 ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael T1 - A structural approach for space compaction for sequential circuits Y1 - 1999 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Synthesis of code-disjoint combinational circuits Y1 - 1997 ER - TY - JOUR A1 - Singh, Adit D. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Seuring, Markus T1 - Testability evaluation of sequential designs incorporating the multi-mode scannable memory element Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael A1 - Morosov, Andrej T1 - A method of construction of combinational self-checking units with detection of all single faults Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Morosov, Andrej T1 - A new totally error propagating compactor for arbitrary cores with digital interfaces Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Morosov, Andrej A1 - Saposhnikov, V. V. A1 - Saposhnikov, VL. V. T1 - Design of combinational self-testing devices with unidirectionally independent outputs Y1 - 1994 ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A scan based concrrent BIST approach for low cost on-line testing Y1 - 1998 ER - TY - JOUR A1 - Dmitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Self-dual sequential circuits for concurrent chechking Y1 - 1999 SN - 0-7695-0390-X ; 0-7695-0391-8 ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A multi-mode scannable memory element for high test application efficiency and delay testing Y1 - 1999 ER - TY - JOUR A1 - Ocheretnij, Vitalij A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel T1 - Modulo p=3 checking for a carry select adder N2 - In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks Y1 - 2006 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-006-6260-8 ER - TY - JOUR A1 - Otscheretnij, Vitalij A1 - Saposhnikov, Vl. V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Fault-tolerant self-dual circuits Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, Vl. V. V. V. A1 - Moshanin, Vl. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Experimental results for self-dual multi-output combinational circuits Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Dimitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. T1 - Eine selbsttestende Struktur zur on-line Fehlererkennung in kombinatorischen Schaltungen Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Ocheretnij, V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Modified TMR-system with reduced hardware overhead Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - New totally self-checking ripple and carry look-ahead adders Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael T1 - A new method of redundancy addition for circuit optimization JF - Preprint / Universität Potsdam, Institut für Informatik Y1 - 1999 SN - 0946-7580 VL - 1999, 08 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - Design of cover circuits for monitoring the output of a MISR Y1 - 1994 SN - 0-8186-6307-3 , 0-8186-6306-5 ER - TY - JOUR A1 - Morosov, Andrej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung Y1 - 1997 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Dimitriev, Alexej A1 - Gössel, Michael A1 - Saposhnikov, Va. V. T1 - Self-dual parity checking - a new method for on-line testing Y1 - 1996 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Kundu, S. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Tarnick, Steffen T1 - Self-checking comparator with one periodiv output Y1 - 1996 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - Code disjoint circuits for partity codes Y1 - 1997 ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - BIST with negligible aliasing through random cover circuits Y1 - 1995 ER - TY - JOUR A1 - Rabenalt, Thomas A1 - Richter, Michael A1 - Pöhl, Frank A1 - Gössel, Michael T1 - Highly efficient test response compaction using a hierarchical x-masking technique JF - IEEE transactions on computer-aided design of integrated circuits and systems N2 - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x. KW - Design for testability (DFT) KW - test response compaction KW - X-masking KW - X-values Y1 - 2012 U6 - https://doi.org/10.1109/TCAD.2011.2181847 SN - 0278-0070 VL - 31 IS - 6 SP - 950 EP - 957 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER - TY - JOUR A1 - Dug, Mehmed A1 - Weidling, Stefan A1 - Sogomonyan, Egor A1 - Jokic, Dejan A1 - Krstić, Miloš T1 - Full error detection and correction method applied on pipelined structure using two approaches JF - Journal of circuits, systems and computers N2 - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach. KW - Fault tolerance KW - FEDC KW - EDC Y1 - 2020 U6 - https://doi.org/10.1142/S0218126620502187 SN - 0218-1266 SN - 1793-6454 VL - 29 IS - 13 PB - World Scientific CY - Singapore ER - TY - JOUR A1 - Li, Yuanqing A1 - Breitenreiter, Anselm A1 - Andjelkovic, Marko A1 - Chen, Junchao A1 - Babic, Milan A1 - Krstić, Miloš T1 - Double cell upsets mitigation through triple modular redundancy JF - Microelectronics Journal N2 - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit. KW - Triple modular redundancy (TMR) KW - Double cell upsets (DCUs) Y1 - 2019 U6 - https://doi.org/10.1016/j.mejo.2019.104683 SN - 0026-2692 SN - 1879-2391 VL - 96 PB - Elsevier CY - Oxford ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Chen, Junchao A1 - Schrape, Oliver A1 - Stamenkovic, Zoran A1 - Krstić, Miloš A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Jaksic, Aleksandar A1 - Vasovic, Nikola A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lallena, Antonio M. A1 - Carvajal, Miguel A. T1 - A design concept for radiation hardened RADFET readout system for space applications JF - Microprocessors and microsystems N2 - Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions. KW - RADFET KW - Radiation hardness KW - Absorbed dose KW - Dose rate KW - Self-adaptive MPSoC Y1 - 2022 U6 - https://doi.org/10.1016/j.micpro.2022.104486 SN - 0141-9331 SN - 1872-9436 VL - 90 PB - Elsevier CY - Amsterdam ER - TY - JOUR A1 - Ristic, Goran S. A1 - Ilic, Stefan D. A1 - Andjelkovic, Marko S. A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lalena, Antonio M. A1 - Krstić, Miloš A1 - Jaksic, Aleksandar B. T1 - Sensitivity and fading of irradiated RADFETs with different gate voltages JF - Nuclear Instruments and Methods in Physics Research Section A N2 - The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters. KW - pMOS radiation dosimeter KW - RADFETs KW - irradiation KW - sensitivity KW - annealing KW - fading Y1 - 2022 U6 - https://doi.org/10.1016/j.nima.2022.166473 SN - 0168-9002 SN - 1872-9576 VL - 1029 PB - Elsevier CY - Amsterdam ER - TY - JOUR A1 - Hilscher, Martin A1 - Braun, Michael A1 - Richter, Michael A1 - Leininger, Andreas A1 - Gössel, Michael T1 - X-tolerant test data compaction with accelerated shift registers N2 - Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution. Y1 - 2009 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-009-5107-5 SN - 0923-8174 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A new self-testing parity checker for ultra-reliable applications Y1 - 1996 ER - TY - JOUR A1 - Tavakoli, Hamad A1 - Alirezazadeh, Pendar A1 - Hedayatipour, Ava A1 - Nasib, A. H. Banijamali A1 - Landwehr, Niels T1 - Leaf image-based classification of some common bean cultivars using discriminative convolutional neural networks JF - Computers and electronics in agriculture : COMPAG online ; an international journal N2 - In recent years, many efforts have been made to apply image processing techniques for plant leaf identification. However, categorizing leaf images at the cultivar/variety level, because of the very low inter-class variability, is still a challenging task. In this research, we propose an automatic discriminative method based on convolutional neural networks (CNNs) for classifying 12 different cultivars of common beans that belong to three various species. We show that employing advanced loss functions, such as Additive Angular Margin Loss and Large Margin Cosine Loss, instead of the standard softmax loss function for the classification can yield better discrimination between classes and thereby mitigate the problem of low inter-class variability. The method was evaluated by classifying species (level I), cultivars from the same species (level II), and cultivars from different species (level III), based on images from the leaf foreside and backside. The results indicate that the performance of the classification algorithm on the leaf backside image dataset is superior. The maximum mean classification accuracies of 95.86, 91.37 and 86.87% were obtained at the levels I, II and III, respectively. The proposed method outperforms the previous relevant works and provides a reliable approach for plant cultivars identification. KW - Bean KW - Plant identification KW - Digital image analysis KW - VGG16 KW - Loss KW - functions Y1 - 2021 U6 - https://doi.org/10.1016/j.compag.2020.105935 SN - 0168-1699 SN - 1872-7107 VL - 181 PB - Elsevier CY - Amsterdam [u.a.] ER - TY - JOUR A1 - Gerber, Stefan A1 - Gössel, Michael T1 - Detection of permanent faults of a floating point adder by pseudoduplication Y1 - 1994 ER -