TY  - JOUR
A1  - Kreowsky, Philipp
A1  - Stabernack, Christian Benno
T1  - A full-featured FPGA-based pipelined architecture for SIFT extraction
JF  - IEEE access : practical research, open solutions / Institute of Electrical and Electronics Engineers
N2  - Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.
KW  - Field programmable gate arrays
KW  - Convolution
KW  - Signal processing
KW  - algorithms
KW  - Kernel
KW  - Image resolution
KW  - Histograms
KW  - Feature extraction
KW  - Scale-invariant feature transform (SIFT)
KW  - field-programmable gate array
KW  - (FPGA)
KW  - image processing
KW  - computer vision
KW  - parallel processing
KW  - architecture
KW  - real-time
KW  - hardware architecture
Y1  - 2021
U6  - https://doi.org/10.1109/ACCESS.2021.3104387
SN  - 2169-3536
VL  - 9
SP  - 128564
EP  - 128573
PB  - Inst. of Electr. and Electronics Engineers
CY  - New York, NY
ER  -