TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - New totally self-checking ripple and carry look-ahead adders Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael T1 - A new method of redundancy addition for circuit optimization JF - Preprint / Universität Potsdam, Institut für Informatik Y1 - 1999 SN - 0946-7580 VL - 1999, 08 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - Design of cover circuits for monitoring the output of a MISR Y1 - 1994 SN - 0-8186-6307-3 , 0-8186-6306-5 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Dimitriev, Alexej A1 - Gössel, Michael A1 - Saposhnikov, Va. V. T1 - Self-dual parity checking - a new method for on-line testing Y1 - 1996 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Kundu, S. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Tarnick, Steffen T1 - Self-checking comparator with one periodiv output Y1 - 1996 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - Code disjoint circuits for partity codes Y1 - 1997 ER - TY - JOUR A1 - Bogue, Ted A1 - Jürgensen, Helmut A1 - Gössel, Michael T1 - BIST with negligible aliasing through random cover circuits Y1 - 1995 ER - TY - JOUR A1 - Rabenalt, Thomas A1 - Richter, Michael A1 - Pöhl, Frank A1 - Gössel, Michael T1 - Highly efficient test response compaction using a hierarchical x-masking technique JF - IEEE transactions on computer-aided design of integrated circuits and systems N2 - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x. KW - Design for testability (DFT) KW - test response compaction KW - X-masking KW - X-values Y1 - 2012 U6 - https://doi.org/10.1109/TCAD.2011.2181847 SN - 0278-0070 VL - 31 IS - 6 SP - 950 EP - 957 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER - TY - JOUR A1 - Dug, Mehmed A1 - Weidling, Stefan A1 - Sogomonyan, Egor A1 - Jokic, Dejan A1 - Krstić, Miloš T1 - Full error detection and correction method applied on pipelined structure using two approaches JF - Journal of circuits, systems and computers N2 - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach. KW - Fault tolerance KW - FEDC KW - EDC Y1 - 2020 U6 - https://doi.org/10.1142/S0218126620502187 SN - 0218-1266 SN - 1793-6454 VL - 29 IS - 13 PB - World Scientific CY - Singapore ER - TY - JOUR A1 - Li, Yuanqing A1 - Breitenreiter, Anselm A1 - Andjelkovic, Marko A1 - Chen, Junchao A1 - Babic, Milan A1 - Krstić, Miloš T1 - Double cell upsets mitigation through triple modular redundancy JF - Microelectronics Journal N2 - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit. KW - Triple modular redundancy (TMR) KW - Double cell upsets (DCUs) Y1 - 2019 U6 - https://doi.org/10.1016/j.mejo.2019.104683 SN - 0026-2692 SN - 1879-2391 VL - 96 PB - Elsevier CY - Oxford ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Chen, Junchao A1 - Schrape, Oliver A1 - Stamenkovic, Zoran A1 - Krstić, Miloš A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Jaksic, Aleksandar A1 - Vasovic, Nikola A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lallena, Antonio M. A1 - Carvajal, Miguel A. T1 - A design concept for radiation hardened RADFET readout system for space applications JF - Microprocessors and microsystems N2 - Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions. KW - RADFET KW - Radiation hardness KW - Absorbed dose KW - Dose rate KW - Self-adaptive MPSoC Y1 - 2022 U6 - https://doi.org/10.1016/j.micpro.2022.104486 SN - 0141-9331 SN - 1872-9436 VL - 90 PB - Elsevier CY - Amsterdam ER - TY - JOUR A1 - Ristic, Goran S. A1 - Ilic, Stefan D. A1 - Andjelkovic, Marko S. A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lalena, Antonio M. A1 - Krstić, Miloš A1 - Jaksic, Aleksandar B. T1 - Sensitivity and fading of irradiated RADFETs with different gate voltages JF - Nuclear Instruments and Methods in Physics Research Section A N2 - The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters. KW - pMOS radiation dosimeter KW - RADFETs KW - irradiation KW - sensitivity KW - annealing KW - fading Y1 - 2022 U6 - https://doi.org/10.1016/j.nima.2022.166473 SN - 0168-9002 SN - 1872-9576 VL - 1029 PB - Elsevier CY - Amsterdam ER - TY - JOUR A1 - Hilscher, Martin A1 - Braun, Michael A1 - Richter, Michael A1 - Leininger, Andreas A1 - Gössel, Michael T1 - X-tolerant test data compaction with accelerated shift registers N2 - Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution. Y1 - 2009 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-009-5107-5 SN - 0923-8174 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A new self-testing parity checker for ultra-reliable applications Y1 - 1996 ER - TY - JOUR A1 - Tavakoli, Hamad A1 - Alirezazadeh, Pendar A1 - Hedayatipour, Ava A1 - Nasib, A. H. Banijamali A1 - Landwehr, Niels T1 - Leaf image-based classification of some common bean cultivars using discriminative convolutional neural networks JF - Computers and electronics in agriculture : COMPAG online ; an international journal N2 - In recent years, many efforts have been made to apply image processing techniques for plant leaf identification. However, categorizing leaf images at the cultivar/variety level, because of the very low inter-class variability, is still a challenging task. In this research, we propose an automatic discriminative method based on convolutional neural networks (CNNs) for classifying 12 different cultivars of common beans that belong to three various species. We show that employing advanced loss functions, such as Additive Angular Margin Loss and Large Margin Cosine Loss, instead of the standard softmax loss function for the classification can yield better discrimination between classes and thereby mitigate the problem of low inter-class variability. The method was evaluated by classifying species (level I), cultivars from the same species (level II), and cultivars from different species (level III), based on images from the leaf foreside and backside. The results indicate that the performance of the classification algorithm on the leaf backside image dataset is superior. The maximum mean classification accuracies of 95.86, 91.37 and 86.87% were obtained at the levels I, II and III, respectively. The proposed method outperforms the previous relevant works and provides a reliable approach for plant cultivars identification. KW - Bean KW - Plant identification KW - Digital image analysis KW - VGG16 KW - Loss KW - functions Y1 - 2021 U6 - https://doi.org/10.1016/j.compag.2020.105935 SN - 0168-1699 SN - 1872-7107 VL - 181 PB - Elsevier CY - Amsterdam [u.a.] ER - TY - JOUR A1 - Gerber, Stefan A1 - Gössel, Michael T1 - Detection of permanent faults of a floating point adder by pseudoduplication Y1 - 1994 ER - TY - JOUR A1 - Bhattacharya, M. K. A1 - Dimitriev, Alexej A1 - Gössel, Michael T1 - Zero-aliasing space compresion using a single periodic output and its application to testing of embedded Y1 - 2000 ER - TY - JOUR A1 - Dimitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Concurrent checking of sequential circuits by alternating inputs Y1 - 1999 ER - TY - JOUR A1 - Kuentzer, Felipe A. A1 - Krstić, Miloš T1 - Soft error detection and correction architecture for asynchronous bundled data designs JF - IEEE transactions on circuits and systems N2 - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%. KW - circuit Faults KW - latches KW - Fault tolerance KW - Fault tolerant systems KW - timing KW - clocks KW - transient analysis KW - asynchrounous design KW - soft errors KW - transient Faults KW - bundled data KW - click controller KW - self-checking KW - concurrent checking KW - DMR KW - TMR Y1 - 2020 U6 - https://doi.org/10.1109/TCSI.2020.2998911 SN - 1549-8328 SN - 1558-0806 VL - 67 IS - 12 SP - 4883 EP - 4894 PB - Institute of Electrical and Electronics Engineers CY - New York ER -