TY - JOUR A1 - Kuentzer, Felipe A. A1 - Krstić, Miloš T1 - Soft error detection and correction architecture for asynchronous bundled data designs JF - IEEE transactions on circuits and systems N2 - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%. KW - circuit Faults KW - latches KW - Fault tolerance KW - Fault tolerant systems KW - timing KW - clocks KW - transient analysis KW - asynchrounous design KW - soft errors KW - transient Faults KW - bundled data KW - click controller KW - self-checking KW - concurrent checking KW - DMR KW - TMR Y1 - 2020 U6 - https://doi.org/10.1109/TCSI.2020.2998911 SN - 1549-8328 SN - 1558-0806 VL - 67 IS - 12 SP - 4883 EP - 4894 PB - Institute of Electrical and Electronics Engineers CY - New York ER -