TY  - JOUR
A1  - Reddy, S. M.
A1  - Kunz, Wolfgang
A1  - Pradhan, D. K.
T1  - Novel verification framework combining structural and OBDD methods in a synthesis environment
Y1  - 1995
SN  - 0-8186-7213-7
SN  - 0-8186-7214-5
ER  - 
TY  - JOUR
A1  - Pradhan, D. K.
A1  - Chatterjee, M.
A1  - Swarna, M.
A1  - Kunz, Wolfgang
T1  - Implication-based gate-level synthesis for low-power
Y1  - 1996
SN  - 0-7803-3571-6
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Reddy, S. M.
A1  - Subodh, M.
A1  - Pradhan, D. K.
T1  - Efficient logic verification in a synthesis environment
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Kunz, Wolfgang
A1  - Pradhan, D. K.
T1  - Recursive learning : a new implication technique for efficient solutions to CAD problems : test, verification and optimization
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Chatterjee, M.
A1  - Pradhan, D. K.
A1  - Kunz, Wolfgang
T1  - ATPG-based Transformations for random-pattern testable logic synthesis
Y1  - 1995
SN  - 0-8186-7213-7
SN  - 0-8186-7214-5
SN  - 0-8186-7215-3
ER  -