TY - GEN A1 - Meinel, Christoph A1 - Sack, Harald T1 - WWW : Kommunikation, Internetworking, Web-Technologien Y1 - 2004 SN - 3-540-44276-6 SN - 1439-5428 PB - Springer CY - Berlin ER - TY - GEN A1 - Marques de Carvalho, Jackson W. A1 - Jürgensen, Helmut T1 - Flexible Structured Mathematics Notation : IADIS, International Conference Interfaces and Human Computer Interaction, Lisabon, 2007 T2 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2007 SN - 0946-7580 VL - 2007, 1 PB - Univ. CY - Potsdam ER - TY - GEN A1 - Stöpel, Christoph A1 - Schubert, Wolfgang A1 - Margaria-Steffen, Tiziana T1 - Plug-ins und Dienste : Ansätze zu Bewältigung zeitvarianter Geschäftsprozesse T2 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2007 SN - 0946-7580 VL - 2007, 2 PB - Univ. CY - Potsdam ER - TY - GEN A1 - Patil, Kaustubh R. A1 - Haider, Peter A1 - Pope, Phillip B. A1 - Turnbaugh, Peter J. A1 - Morrison, Mark A1 - Scheffer, Tobias A1 - McHardy, Alice C. T1 - Taxonomic metagenome sequence assignment with structured output models T2 - Nature methods : techniques for life scientists and chemists Y1 - 2011 U6 - https://doi.org/10.1038/nmeth0311-191 SN - 1548-7091 VL - 8 IS - 3 SP - 191 EP - 192 PB - Nature Publ. Group CY - London ER - TY - GEN ED - Plattner, Hasso ED - Meinel, Christoph ED - Leifer, Larry T1 - Design thinking : understand - improve - apply Y1 - 2011 SN - 978-3-642-13756-3 PB - Springer-Verlag Berlin Heidelberg CY - Berlin, Heidelberg ER - TY - GEN A1 - Giese, Holger ED - Kouchnarenko, Olga ED - Khosravi, Ramtin T1 - Formal models and analysis for self-adaptive cyber-physical systems BT - (extended abstract) T2 - Lecture notes in computer science N2 - In this extended abstract, we will analyze the current challenges for the envisioned Self-Adaptive CPS. In addition, we will outline our results to approach these challenges with SMARTSOS [10] a generic approach based on extensions of graph transformation systems employing open and adaptive collaborations and models at runtime for trustworthy self-adaptation, self-organization, and evolution of the individual systems and the system-of-systems level taking the independent development, operation, management, and evolution of these systems into account. Y1 - 2017 SN - 978-3-319-57666-4 SN - 978-3-319-57665-7 U6 - https://doi.org/10.1007/978-3-319-57666-4_1 SN - 0302-9743 SN - 1611-3349 VL - 10231 SP - 3 EP - 9 PB - Springer CY - Cham ER - TY - GEN A1 - Saint-Dizier, Patrick A1 - Stede, Manfred T1 - Foundations of the language of argumentation T2 - Argument & computation Y1 - 2017 U6 - https://doi.org/10.3233/AAC-170018 SN - 1946-2166 SN - 1946-2174 VL - 8 IS - 2 Special issue SP - 91 EP - 93 PB - IOS Press CY - Amsterdam ER - TY - GEN A1 - Fabian, Benjamin A1 - Baumann, Annika A1 - Ehlert, Mathias A1 - Ververis, Vasilis A1 - Ermakova, Tatiana T1 - CORIA - Analyzing internet connectivity risks using network graphs T2 - 2017 IEEE International Conference on Communications (ICC) N2 - The Internet can be considered as the most important infrastructure for modern society and businesses. A loss of Internet connectivity has strong negative financial impacts for businesses and economies. Therefore, assessing Internet connectivity, in particular beyond their own premises and area of direct control, is of growing importance in the face of potential failures, accidents, and malicious attacks. This paper presents CORIA, a software framework for an easy analysis of connectivity risks based on large network graphs. It provides researchers, risk analysts, network managers and security consultants with a tool to assess an organization's connectivity and paths options through the Internet backbone, including a user-friendly and insightful visual representation of results. CORIA is flexibly extensible in terms of novel data sets, graph metrics, and risk scores that enable further use cases. The performance of CORIA is evaluated by several experiments on the Internet graph and further randomly generated networks. KW - risk analysis KW - connectivity KW - graph analysis KW - complex networks KW - Internet Y1 - 2017 SN - 978-1-4673-8999-0 SN - 978-1-4673-9000-2 U6 - https://doi.org/10.1109/ICC.2017.7996828 SN - 1550-3607 PB - IEEE CY - Piscataway ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Schölzel, Mario T1 - On hardware-based fault-handling in dynamically scheduled processors T2 - 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2017 N2 - This paper describes architectural extensions for a dynamically scheduled processor, so that it can be used in three different operation modes, ranging from high-performance, to high-reliability. With minor hardware-extensions of the control path, the resources of the superscalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. This makes the processor-architecture a very good candidate for applications with dynamically changing reliability requirements, e.g. for automotive applications. The paper reports the hardware-overhead for the extensions, and investigates the performance penalties introduced by the fail-safe and fault-tolerant mode. Furthermore, a comprehensive fault simulation was carried out in order to investigate the fault-coverage of the proposed approach. Y1 - 2017 SN - 978-1-5386-0472-4 U6 - https://doi.org/10.1109/DDECS.2017.7934572 SN - 2334-3133 SN - 2473-2117 SP - 201 EP - 206 PB - IEEE CY - New York ER - TY - GEN A1 - Mühlbauer, Felix A1 - Schröder, Lukas A1 - Skoncej, Patryk A1 - Schölzel, Mario T1 - Handling manufacturing and aging faults with software-based techniques in tiny embedded systems T2 - 18th IEEE Latin American Test Symposium (LATS 2017) N2 - Non-volatile memory area occupies a large portion of the area of a chip in an embedded system. Such memories are prone to manufacturing faults, retention faults, and aging faults. The paper presents a single software based technique that allows for handling all of these fault types in tiny embedded systems without the need for hardware support. This is beneficial for low-cost embedded systems with simple memory architectures. A software infrastructure and a flow are presented that demonstrate how the presented technique is used in general for fault handling right after manufacturing and in-the-field. Moreover, a full implementation is presented for a MSP430 microcontroller, along with a discussion of the performance, overhead, and reliability impacts. Y1 - 2027 SN - 978-1-5386-0415-1 U6 - https://doi.org/10.1109/LATW.2017.7906756 PB - IEEE CY - New York ER -