TY  - JOUR
A1  - Bogue, Ted
A1  - Jürgensen, Helmut
A1  - Gössel, Michael
T1  - Design of cover circuits for monitoring the output of a MISR
Y1  - 1994
SN  - 0-8186-6307-3 , 0-8186-6306-5
ER  - 
TY  - JOUR
A1  - Morosov, Andrej
A1  - Saposhnikov, V. V.
A1  - Saposhnikov, Vl. V.
A1  - Gössel, Michael
T1  - Ein Transformationsalgorithmus einer kombinatorischen Schaltung in eine monotone Schaltung
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Saposhnikov, Vl. V.
A1  - Dimitriev, Alexej
A1  - Gössel, Michael
A1  - Saposhnikov, Va. V.
T1  - Self-dual parity checking - a new method for on-line testing
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design
Y1  - 1994
ER  - 
TY  - JOUR
A1  - Kundu, S.
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
A1  - Tarnick, Steffen
T1  - Self-checking comparator with one periodiv output
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Hartje, Hendrik
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
T1  - Code disjoint circuits for partity codes
Y1  - 1997
ER  - 
TY  - JOUR
A1  - Bogue, Ted
A1  - Jürgensen, Helmut
A1  - Gössel, Michael
T1  - BIST with negligible aliasing through random cover circuits
Y1  - 1995
ER  - 
TY  - JOUR
A1  - Rabenalt, Thomas
A1  - Richter, Michael
A1  - Pöhl, Frank
A1  - Gössel, Michael
T1  - Highly efficient test response compaction using a hierarchical x-masking technique
JF  - IEEE transactions on computer-aided design of integrated circuits and systems
N2  - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.
KW  - Design for testability (DFT)
KW  - test response compaction
KW  - X-masking
KW  - X-values
Y1  - 2012
U6  - https://doi.org/10.1109/TCAD.2011.2181847
SN  - 0278-0070
VL  - 31
IS  - 6
SP  - 950
EP  - 957
PB  - Inst. of Electr. and Electronics Engineers
CY  - Piscataway
ER  - 
TY  - JOUR
A1  - Dug, Mehmed
A1  - Weidling, Stefan
A1  - Sogomonyan, Egor
A1  - Jokic, Dejan
A1  - Krstić, Miloš
T1  - Full error detection and correction method applied on pipelined structure using two approaches
JF  - Journal of circuits, systems and computers
N2  - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.
KW  - Fault tolerance
KW  - FEDC
KW  - EDC
Y1  - 2020
U6  - https://doi.org/10.1142/S0218126620502187
SN  - 0218-1266
SN  - 1793-6454
VL  - 29
IS  - 13
PB  - World Scientific
CY  - Singapore
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Breitenreiter, Anselm
A1  - Andjelkovic, Marko
A1  - Chen, Junchao
A1  - Babic, Milan
A1  - Krstić, Miloš
T1  - Double cell upsets mitigation through triple modular redundancy
JF  - Microelectronics Journal
N2  - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.
KW  - Triple modular redundancy (TMR)
KW  - Double cell upsets (DCUs)
Y1  - 2019
U6  - https://doi.org/10.1016/j.mejo.2019.104683
SN  - 0026-2692
SN  - 1879-2391
VL  - 96
PB  - Elsevier
CY  - Oxford
ER  -