TY  - JOUR
A1  - Bhattacharya, M. K.
A1  - Dimitriev, Alexej
A1  - Gössel, Michael
T1  - Zero-aliasing space compresion using a single periodic output and its application to testing of embedded
Y1  - 2000
ER  - 
TY  - JOUR
A1  - Dimitriev, Alexej
A1  - Saposhnikov, V. V.
A1  - Saposhnikov, Vl. V.
A1  - Gössel, Michael
T1  - Concurrent checking of sequential circuits by alternating inputs
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Kuentzer, Felipe A.
A1  - Krstić, Miloš
T1  - Soft error detection and correction architecture for asynchronous bundled data designs
JF  - IEEE transactions on circuits and systems
N2  - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%.
KW  - circuit Faults
KW  - latches
KW  - Fault tolerance
KW  - Fault tolerant systems
KW  - timing
KW  - clocks
KW  - transient analysis
KW  - asynchrounous design
KW  - soft errors
KW  - transient Faults
KW  - bundled data
KW  - click controller
KW  - self-checking
KW  - concurrent checking
KW  - DMR
KW  - TMR
Y1  - 2020
U6  - https://doi.org/10.1109/TCSI.2020.2998911
SN  - 1549-8328
SN  - 1558-0806
VL  - 67
IS  - 12
SP  - 4883
EP  - 4894
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  - 
TY  - JOUR
A1  - Saposhnikov, Vl. V.
A1  - Otscheretnij, Vitalij
A1  - Saposhnikov, V. V.
A1  - Gössel, Michael
T1  - Design of Fault-Tolerant Circuits by self-dual Duplication
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Moschanin, Wladimir
A1  - Saposhnikov, Vl. V.
A1  - Saposhnikov, Va. V.
A1  - Gössel, Michael
T1  - Synthesis of self-dual multi-output combinational circuits for on-line Teting
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Seuring, Markus
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - Ein strukturelles Verfahren zur Kompaktierung von Schaltungsausgaben für online-Fehlererkennungen und Selbstests
Y1  - 1998
ER  - 
TY  - JOUR
A1  - Sogomonyan, Egor S.
A1  - Gössel, Michael
T1  - Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
Y1  - 1996
ER  - 
TY  - JOUR
A1  - Morosov, Andrej
A1  - Gössel, Michael
A1  - Hartje, Hendrik
T1  - Reduced area overhead of the input party for code-disjoint circuits
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Seuring, Markus
A1  - Gössel, Michael
T1  - A structural method for output compaction of sequential automata implemented as circuits
Y1  - 1999
ER  - 
TY  - JOUR
A1  - Hlawiczka, A.
A1  - Gössel, Michael
A1  - Sogomonyan, Egor S.
T1  - A linear code-preserving signature analyzer COPMISR
Y1  - 1997
SN  - 0-8186-7810-0
ER  -