TY  - JOUR
A1  - Li, Yuanqing
A1  - Chen, Li
A1  - Nofal, Issam
A1  - Chen, Mo
A1  - Wang, Haibin
A1  - Liu, Rui
A1  - Chen, Qingyu
A1  - Krstić, Miloš
A1  - Shi, Shuting
A1  - Guo, Gang
A1  - Baeg, Sang H.
A1  - Wen, Shi-Jie
A1  - Wong, Richard
T1  - Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree
JF  - Microelectronics reliability
N2  - The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.
KW  - Clock tree
KW  - Modeling
KW  - Single-event transient (SET)
Y1  - 2018
U6  - https://doi.org/10.1016/j.microrel.2018.05.016
SN  - 0026-2714
VL  - 87
SP  - 24
EP  - 32
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - GEN
A1  - Andjelkovic, Marko
A1  - Babic, Milan
A1  - Li, Yuanqing
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Kraemer, Rolf
T1  - Use of decoupling cells for mitigation of SET effects in CMOS combinational gates
T2  - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
N2  - This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles.
KW  - decoupling cells
KW  - radiation hardening
KW  - SET effects
KW  - CMOS technology
KW  - combinational logic
Y1  - 2019
SN  - 978-1-5386-9562-3
U6  - https://doi.org/10.1109/ICECS.2018.8617996
SP  - 361
EP  - 364
PB  - IEEE
CY  - New York
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Breitenreiter, Anselm
A1  - Andjelkovic, Marko
A1  - Chen, Junchao
A1  - Babic, Milan
A1  - Krstić, Miloš
T1  - Double cell upsets mitigation through triple modular redundancy
JF  - Microelectronics Journal
N2  - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.
KW  - Triple modular redundancy (TMR)
KW  - Double cell upsets (DCUs)
Y1  - 2019
U6  - https://doi.org/10.1016/j.mejo.2019.104683
SN  - 0026-2692
SN  - 1879-2391
VL  - 96
PB  - Elsevier
CY  - Oxford
ER  -