TY - JOUR A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Chen, Junchao A1 - Schrape, Oliver A1 - Stamenkovic, Zoran A1 - Krstić, Miloš A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Jaksic, Aleksandar A1 - Vasovic, Nikola A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lallena, Antonio M. A1 - Carvajal, Miguel A. T1 - A design concept for radiation hardened RADFET readout system for space applications JF - Microprocessors and microsystems N2 - Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions. KW - RADFET KW - Radiation hardness KW - Absorbed dose KW - Dose rate KW - Self-adaptive MPSoC Y1 - 2022 U6 - https://doi.org/10.1016/j.micpro.2022.104486 SN - 0141-9331 SN - 1872-9436 VL - 90 PB - Elsevier CY - Amsterdam ER - TY - JOUR A1 - Ristic, Goran S. A1 - Ilic, Stefan D. A1 - Andjelkovic, Marko S. A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lalena, Antonio M. A1 - Krstić, Miloš A1 - Jaksic, Aleksandar B. T1 - Sensitivity and fading of irradiated RADFETs with different gate voltages JF - Nuclear Instruments and Methods in Physics Research Section A N2 - The radiation-sensitive field-effect transistors (RADFETs) with an oxide thickness of 400 nm are irradiated with gate voltages of 2, 4 and 6 V, and without gate voltage. A detailed analysis of the mechanisms responsible for the creation of traps during irradiation is performed. The creation of the traps in the oxide, near and at the silicon/silicon-dioxide (Si/SiO2) interface during irradiation is modelled very well. This modelling can also be used for other MOS transistors containing SiO2. The behaviour of radiation traps during postirradiation annealing is analysed, and the corresponding functions for their modelling are obtained. The switching traps (STs) do not have significant influence on threshold voltage shift, and two radiation-induced trap types fit the fixed traps (FTs) very well. The fading does not depend on the positive gate voltage applied during irradiation, but it is twice lower in case there is no gate voltage. A new dosimetric parameter, called the Golden Ratio (GR), is proposed, which represents the ratio between the threshold voltage shift after irradiation and fading after spontaneous annealing. This parameter can be useful for comparing MOS dosimeters. KW - pMOS radiation dosimeter KW - RADFETs KW - irradiation KW - sensitivity KW - annealing KW - fading Y1 - 2022 U6 - https://doi.org/10.1016/j.nima.2022.166473 SN - 0168-9002 SN - 1872-9576 VL - 1029 PB - Elsevier CY - Amsterdam ER - TY - BOOK A1 - Rana, Kaushik A1 - Mohapatra, Durga Prasad A1 - Sidorova, Julia A1 - Lundberg, Lars A1 - Sköld, Lars A1 - Lopes Grim, Luís Fernando A1 - Sampaio Gradvohl, André Leon A1 - Cremerius, Jonas A1 - Siegert, Simon A1 - Weltzien, Anton von A1 - Baldi, Annika A1 - Klessascheck, Finn A1 - Kalancha, Svitlana A1 - Lichtenstein, Tom A1 - Shaabani, Nuhad A1 - Meinel, Christoph A1 - Friedrich, Tobias A1 - Lenzner, Pascal A1 - Schumann, David A1 - Wiese, Ingmar A1 - Sarna, Nicole A1 - Wiese, Lena A1 - Tashkandi, Araek Sami A1 - van der Walt, Estée A1 - Eloff, Jan H. P. A1 - Schmidt, Christopher A1 - Hügle, Johannes A1 - Horschig, Siegfried A1 - Uflacker, Matthias A1 - Najafi, Pejman A1 - Sapegin, Andrey A1 - Cheng, Feng A1 - Stojanovic, Dragan A1 - Stojnev Ilić, Aleksandra A1 - Djordjevic, Igor A1 - Stojanovic, Natalija A1 - Predic, Bratislav A1 - González-Jiménez, Mario A1 - de Lara, Juan A1 - Mischkewitz, Sven A1 - Kainz, Bernhard A1 - van Hoorn, André A1 - Ferme, Vincenzo A1 - Schulz, Henning A1 - Knigge, Marlene A1 - Hecht, Sonja A1 - Prifti, Loina A1 - Krcmar, Helmut A1 - Fabian, Benjamin A1 - Ermakova, Tatiana A1 - Kelkel, Stefan A1 - Baumann, Annika A1 - Morgenstern, Laura A1 - Plauth, Max A1 - Eberhard, Felix A1 - Wolff, Felix A1 - Polze, Andreas A1 - Cech, Tim A1 - Danz, Noel A1 - Noack, Nele Sina A1 - Pirl, Lukas A1 - Beilharz, Jossekin Jakob A1 - De Oliveira, Roberto C. L. A1 - Soares, Fábio Mendes A1 - Juiz, Carlos A1 - Bermejo, Belen A1 - Mühle, Alexander A1 - Grüner, Andreas A1 - Saxena, Vageesh A1 - Gayvoronskaya, Tatiana A1 - Weyand, Christopher A1 - Krause, Mirko A1 - Frank, Markus A1 - Bischoff, Sebastian A1 - Behrens, Freya A1 - Rückin, Julius A1 - Ziegler, Adrian A1 - Vogel, Thomas A1 - Tran, Chinh A1 - Moser, Irene A1 - Grunske, Lars A1 - Szárnyas, Gábor A1 - Marton, József A1 - Maginecz, János A1 - Varró, Dániel A1 - Antal, János Benjamin ED - Meinel, Christoph ED - Polze, Andreas ED - Beins, Karsten ED - Strotmann, Rolf ED - Seibold, Ulrich ED - Rödszus, Kurt ED - Müller, Jürgen T1 - HPI Future SOC Lab – Proceedings 2018 N2 - The “HPI Future SOC Lab” is a cooperation of the Hasso Plattner Institute (HPI) and industry partners. Its mission is to enable and promote exchange and interaction between the research community and the industry partners. The HPI Future SOC Lab provides researchers with free of charge access to a complete infrastructure of state of the art hard and software. This infrastructure includes components, which might be too expensive for an ordinary research environment, such as servers with up to 64 cores and 2 TB main memory. The offerings address researchers particularly from but not limited to the areas of computer science and business information systems. Main areas of research include cloud computing, parallelization, and In-Memory technologies. This technical report presents results of research projects executed in 2018. Selected projects have presented their results on April 17th and November 14th 2017 at the Future SOC Lab Day events. N2 - Das Future SOC Lab am HPI ist eine Kooperation des Hasso-Plattner-Instituts mit verschiedenen Industriepartnern. Seine Aufgabe ist die Ermöglichung und Förderung des Austausches zwischen Forschungsgemeinschaft und Industrie. Am Lab wird interessierten Wissenschaftler:innen eine Infrastruktur von neuester Hard- und Software kostenfrei für Forschungszwecke zur Verfügung gestellt. Dazu zählen Systeme, die im normalen Hochschulbereich in der Regel nicht zu finanzieren wären, bspw. Server mit bis zu 64 Cores und 2 TB Hauptspeicher. Diese Angebote richten sich insbesondere an Wissenschaftler:innen in den Gebieten Informatik und Wirtschaftsinformatik. Einige der Schwerpunkte sind Cloud Computing, Parallelisierung und In-Memory Technologien. In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2018 vorgestellt. Ausgewählte Projekte stellten ihre Ergebnisse am 17. April und 14. November 2018 im Rahmen des Future SOC Lab Tags vor. T3 - Technische Berichte des Hasso-Plattner-Instituts für Digital Engineering an der Universität Potsdam - 151 KW - Future SOC Lab KW - research projects KW - multicore architectures KW - in-memory technology KW - cloud computing KW - machine learning KW - artifical intelligence KW - Future SOC Lab KW - Forschungsprojekte KW - Multicore Architekturen KW - In-Memory Technologie KW - Cloud Computing KW - maschinelles Lernen KW - künstliche Intelligenz Y1 - 2022 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:517-opus4-563712 SN - 978-3-86956-547-7 SN - 1613-5652 SN - 2191-1665 IS - 151 PB - Universitätsverlag Potsdam CY - Potsdam ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Marjanovic, Milos A1 - Drasko, Bojan A1 - Calligaro, Cristiano A1 - Schrape, Oliver A1 - Gatti, Umberto A1 - Kuentzer, Felipe A. A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Krstić, Miloš T1 - Analysis of single event transient effects in standard delay cells based on decoupling capacitors JF - Journal of circuits, systems, and computers : JCSC N2 - Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter. KW - single event transients KW - standard delay cells KW - decoupling capacitors Y1 - 2022 U6 - https://doi.org/10.1142/S0218126622400072 SN - 0218-1266 SN - 1793-6454 VL - 31 IS - 18 PB - World Scientific CY - Singapore [u.a.] ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Marjanovic, Milos A1 - Chen, Junchao A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Krstic, Milos T1 - PS-BBICS: Pulse stretching bulk built-in current sensor for on-chip measurement of single event transients JF - Microelectronics reliability N2 - The bulk built-in current sensor (BBICS) is a cost-effective solution for detection of energetic particle strikes in integrated circuits. With an appropriate number of BBICSs distributed across the chip, the soft error locations can be identified, and the dynamic fault-tolerant mechanisms can be activated locally to correct the soft errors in the affected logic. In this work, we introduce a pulse stretching BBICS (PS-BBICS) constructed by connecting a standard BBICS and a custom-designed pulse stretching cell. The aim of PS-BBICS is to enable the on-chip measurement of the single event transient (SET) pulse width, allowing to detect the linear energy transfer (LET) of incident particles, and thus assess more accurately the radiation conditions. Based on Spectre simula-tions, we have shown that for the LET from 1 to 100 MeV cm2 mg -1, the SET pulse width detected by PS-BBICS varies by 620-800 ps. The threshold LET of PS-BBICS increases linearly with the number of monitored inverters, and it is around 1.7 MeV cm2 mg- 1 for ten monitored inverters. On the other hand, the SET pulse width is in-dependent of the number of monitored inverters for LET > 4 MeV cm2 mg -1. It was shown that supply voltage, temperature and process variations have strong impact on the response of PS-BBICS. KW - bulk built-in current sensor KW - single event transients KW - soft errors Y1 - 2022 U6 - https://doi.org/10.1016/j.microrel.2022.114726 SN - 0026-2714 SN - 1872-941X VL - 138 PB - Elsevier CY - Amsterdam [u.a.] ER -