TY - JOUR A1 - Andjelkovic, Marko A1 - Marjanovic, Milos A1 - Drasko, Bojan A1 - Calligaro, Cristiano A1 - Schrape, Oliver A1 - Gatti, Umberto A1 - Kuentzer, Felipe A. A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Krstić, Miloš T1 - Analysis of single event transient effects in standard delay cells based on decoupling capacitors JF - Journal of circuits, systems, and computers : JCSC N2 - Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter. KW - single event transients KW - standard delay cells KW - decoupling capacitors Y1 - 2022 U6 - https://doi.org/10.1142/S0218126622400072 SN - 0218-1266 SN - 1793-6454 VL - 31 IS - 18 PB - World Scientific CY - Singapore [u.a.] ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Marjanovic, Milos A1 - Chen, Junchao A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Krstic, Milos T1 - PS-BBICS: Pulse stretching bulk built-in current sensor for on-chip measurement of single event transients JF - Microelectronics reliability N2 - The bulk built-in current sensor (BBICS) is a cost-effective solution for detection of energetic particle strikes in integrated circuits. With an appropriate number of BBICSs distributed across the chip, the soft error locations can be identified, and the dynamic fault-tolerant mechanisms can be activated locally to correct the soft errors in the affected logic. In this work, we introduce a pulse stretching BBICS (PS-BBICS) constructed by connecting a standard BBICS and a custom-designed pulse stretching cell. The aim of PS-BBICS is to enable the on-chip measurement of the single event transient (SET) pulse width, allowing to detect the linear energy transfer (LET) of incident particles, and thus assess more accurately the radiation conditions. Based on Spectre simula-tions, we have shown that for the LET from 1 to 100 MeV cm2 mg -1, the SET pulse width detected by PS-BBICS varies by 620-800 ps. The threshold LET of PS-BBICS increases linearly with the number of monitored inverters, and it is around 1.7 MeV cm2 mg- 1 for ten monitored inverters. On the other hand, the SET pulse width is in-dependent of the number of monitored inverters for LET > 4 MeV cm2 mg -1. It was shown that supply voltage, temperature and process variations have strong impact on the response of PS-BBICS. KW - bulk built-in current sensor KW - single event transients KW - soft errors Y1 - 2022 U6 - https://doi.org/10.1016/j.microrel.2022.114726 SN - 0026-2714 SN - 1872-941X VL - 138 PB - Elsevier CY - Amsterdam [u.a.] ER - TY - JOUR A1 - Chen, Junchao A1 - Lange, Thomas A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Lu, Li A1 - Krstić, Miloš T1 - Solar particle event and single event upset prediction from SRAM-based monitor and supervised machine learning JF - IEEE transactions on emerging topics in computing / IEEE Computer Society, Institute of Electrical and Electronics Engineers N2 - The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels. KW - Machine learning KW - Single event upsets KW - Random access memory KW - monitoring KW - machine learning algorithms KW - predictive models KW - space missions KW - solar particle event KW - single event upset KW - machine learning KW - online learning KW - hardware accelerator KW - reliability KW - self-adaptive multiprocessing system Y1 - 2022 U6 - https://doi.org/10.1109/TETC.2022.3147376 SN - 2168-6750 VL - 10 IS - 2 SP - 564 EP - 580 PB - Institute of Electrical and Electronics Engineers CY - [New York, NY] ER - TY - JOUR A1 - Schrape, Oliver A1 - Andjelkovic, Marko A1 - Breitenreiter, Anselm A1 - Zeidler, Steffen A1 - Balashov, Alexey A1 - Krstić, Miloš T1 - Design and evaluation of radiation-hardened standard cell flip-flops JF - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers N2 - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant. KW - Single event effect KW - fault tolerance KW - triple modular redundancy KW - ASIC KW - design flow KW - radhard design Y1 - 2021 U6 - https://doi.org/10.1109/TCSI.2021.3109080 SN - 1549-8328 SN - 1558-0806 SN - 1057-7122 VL - 68 IS - 11 SP - 4796 EP - 4809 PB - Inst. of Electr. and Electronics Engineers CY - New York, NY ER - TY - GEN A1 - Andjelkovic, Marko A1 - Babic, Milan A1 - Li, Yuanqing A1 - Schrape, Oliver A1 - Krstić, Miloš A1 - Kraemer, Rolf T1 - Use of decoupling cells for mitigation of SET effects in CMOS combinational gates T2 - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS) N2 - This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles. KW - decoupling cells KW - radiation hardening KW - SET effects KW - CMOS technology KW - combinational logic Y1 - 2019 SN - 978-1-5386-9562-3 U6 - https://doi.org/10.1109/ICECS.2018.8617996 SP - 361 EP - 364 PB - IEEE CY - New York ER - TY - JOUR A1 - Li, Yuanqing A1 - Breitenreiter, Anselm A1 - Andjelkovic, Marko A1 - Chen, Junchao A1 - Babic, Milan A1 - Krstić, Miloš T1 - Double cell upsets mitigation through triple modular redundancy JF - Microelectronics Journal N2 - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit. KW - Triple modular redundancy (TMR) KW - Double cell upsets (DCUs) Y1 - 2019 U6 - https://doi.org/10.1016/j.mejo.2019.104683 SN - 0026-2692 SN - 1879-2391 VL - 96 PB - Elsevier CY - Oxford ER - TY - JOUR A1 - Andjelkovic, Marko A1 - Simevski, Aleksandar A1 - Chen, Junchao A1 - Schrape, Oliver A1 - Stamenkovic, Zoran A1 - Krstić, Miloš A1 - Ilic, Stefan A1 - Ristic, Goran A1 - Jaksic, Aleksandar A1 - Vasovic, Nikola A1 - Duane, Russell A1 - Palma, Alberto J. A1 - Lallena, Antonio M. A1 - Carvajal, Miguel A. T1 - A design concept for radiation hardened RADFET readout system for space applications JF - Microprocessors and microsystems N2 - Instruments for measuring the absorbed dose and dose rate under radiation exposure, known as radiation dosimeters, are indispensable in space missions. They are composed of radiation sensors that generate current or voltage response when exposed to ionizing radiation, and processing electronics for computing the absorbed dose and dose rate. Among a wide range of existing radiation sensors, the Radiation Sensitive Field Effect Transistors (RADFETs) have unique advantages for absorbed dose measurement, and a proven record of successful exploitation in space missions. It has been shown that the RADFETs may be also used for the dose rate monitoring. In that regard, we propose a unique design concept that supports the simultaneous operation of a single RADFET as absorbed dose and dose rate monitor. This enables to reduce the cost of implementation, since the need for other types of radiation sensors can be minimized or eliminated. For processing the RADFET's response we propose a readout system composed of analog signal conditioner (ASC) and a self-adaptive multiprocessing system-on-chip (MPSoC). The soft error rate of MPSoC is monitored in real time with embedded sensors, allowing the autonomous switching between three operating modes (high-performance, de-stress and fault-tolerant), according to the application requirements and radiation conditions. KW - RADFET KW - Radiation hardness KW - Absorbed dose KW - Dose rate KW - Self-adaptive MPSoC Y1 - 2022 U6 - https://doi.org/10.1016/j.micpro.2022.104486 SN - 0141-9331 SN - 1872-9436 VL - 90 PB - Elsevier CY - Amsterdam ER -