TY - BOOK A1 - Goessel, Michael A1 - Ocheretny, Vitaly A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel T1 - New methods of concurrent checking T3 - Frontiers in electronic testing Y1 - 2008 SN - 978-1-402-08419-5 U6 - https://doi.org/10.1007/978-1-4020-8420-1 VL - 42 PB - Springer CY - Dordrecht; Heidelberg ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A structural approach for space compaction for concurrent checking and BIST Y1 - 1998 ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - A new parity preserving multi-input signature analyser Y1 - 1995 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A parity-preserving multi-input signature analyzer and it application for concurrent checking and BIST Y1 - 1996 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Synthesis of code-disjoint combinational circuits Y1 - 1997 ER - TY - JOUR A1 - Singh, Adit D. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Seuring, Markus T1 - Testability evaluation of sequential designs incorporating the multi-mode scannable memory element Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Self-parity combinational-circuits for self-testing, concurrent fault-detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Morosov, Andrej T1 - A new totally error propagating compactor for arbitrary cores with digital interfaces Y1 - 1999 ER - TY - BOOK A1 - Marienfeld, Daniel A1 - Sogomonyan, Egor S. A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - Self-checking Output-duplicated Booth-2 Multiplier T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2005 SN - 0946-7580 VL - 2005, 1 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A scan based concrrent BIST approach for low cost on-line testing Y1 - 1998 ER - TY - BOOK A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel A1 - Gössel, Michael T1 - Fehlerkorrektur und Fehlererkennung T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2006 SN - 0946-7580 VL - 2006, 3 PB - Univ. CY - Potsdam ER - TY - BOOK A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - A new self-checking sum-bit duplicated carry-select adder T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2003 SN - 0946-7580 VL - 2003, 5 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Sogomonyan, Egor S. A1 - Singh, Adit D. A1 - Gössel, Michael T1 - A multi-mode scannable memory element for high test application efficiency and delay testing Y1 - 1999 ER - TY - JOUR A1 - Ocheretnij, Vitalij A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel T1 - Modulo p=3 checking for a carry select adder N2 - In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks Y1 - 2006 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-006-6260-8 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - New totally self-checking ripple and carry look-ahead adders Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design Y1 - 1994 ER - TY - JOUR A1 - Kundu, S. A1 - Sogomonyan, Egor S. A1 - Gössel, Michael A1 - Tarnick, Steffen T1 - Self-checking comparator with one periodiv output Y1 - 1996 ER - TY - JOUR A1 - Hartje, Hendrik A1 - Sogomonyan, Egor S. A1 - Gössel, Michael T1 - Code disjoint circuits for partity codes Y1 - 1997 ER - TY - JOUR A1 - Dug, Mehmed A1 - Weidling, Stefan A1 - Sogomonyan, Egor A1 - Jokic, Dejan A1 - Krstić, Miloš T1 - Full error detection and correction method applied on pipelined structure using two approaches JF - Journal of circuits, systems and computers N2 - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach. KW - Fault tolerance KW - FEDC KW - EDC Y1 - 2020 U6 - https://doi.org/10.1142/S0218126620502187 SN - 0218-1266 SN - 1793-6454 VL - 29 IS - 13 PB - World Scientific CY - Singapore ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - A new self-testing parity checker for ultra-reliable applications Y1 - 1996 ER -