TY  - JOUR
A1  - Fan, Xin
A1  - Stegmann, Mikkel B.
A1  - Schrappe, Oliver
A1  - Zeidler, Steffen
A1  - Jensen, Isac G.
A1  - Thorsen, Jannich
A1  - Bjerregaard, Tobias
A1  - Krstić, Miloš
T1  - Frequency-domain optimization of digital switching noise based on clock scheduling
JF  - IEEE Transactions on Circuits and Systems I
N2  - The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.
Y1  - 2016
U6  - https://doi.org/10.1109/TCSI.2016.2546118
SN  - 1549-8328
VL  - 63
IS  - 7
SP  - 982
EP  - 993
ER  -