TY  - GEN
A1  - Herzog, Benedict
A1  - Hönig, Timo
A1  - Schröder-Preikschat, Wolfgang
A1  - Plauth, Max
A1  - Köhler, Sven
A1  - Polze, Andreas
T1  - Bridging the Gap
BT  - Energy-efficient Execution of Software Workloads on Heterogeneous Hardware Components
T2  - e-Energy '19: Proceedings of the Tenth ACM International Conference on Future Energy Systems
N2  - The recent restructuring of the electricity grid (i.e., smart grid) introduces a number of challenges for today's large-scale computing systems. To operate reliable and efficient, computing systems must adhere not only to technical limits (i.e., thermal constraints) but they must also reduce operating costs, for example, by increasing their energy efficiency. Efforts to improve the energy efficiency, however, are often hampered by inflexible software components that hardly adapt to underlying hardware characteristics. In this paper, we propose an approach to bridge the gap between inflexible software and heterogeneous hardware architectures. Our proposal introduces adaptive software components that dynamically adapt to heterogeneous processing units (i.e., accelerators) during runtime to improve the energy efficiency of computing systems.
Y1  - 2019
SN  - 978-1-4503-6671-7
U6  - https://doi.org/10.1145/3307772.3330176
SP  - 428
EP  - 430
PB  - Association for Computing Machinery
CY  - New York
ER  - 
TY  - GEN
A1  - Plauth, Max
A1  - Polze, Andreas
T1  - Towards improving data transfer efficiency for accelerators using hardware compression
T2  - Sixth International Symposium on Computing and Networking Workshops (CANDARW)
N2  - The overhead of moving data is the major limiting factor in todays hardware, especially in heterogeneous systems where data needs to be transferred frequently between host and accelerator memory. With the increasing availability of hardware-based compression facilities in modern computer architectures, this paper investigates the potential of hardware-accelerated I/O Link Compression as a promising approach to reduce data volumes and transfer time, thus improving the overall efficiency of accelerators in heterogeneous systems. Our considerations are focused on On-the-Fly compression in both Single-Node and Scale-Out deployments. Based on a theoretical analysis, this paper demonstrates the feasibility of hardware-accelerated On-the-Fly I/O Link Compression for many workloads in a Scale-Out scenario, and for some even in a Single-Node scenario. These findings are confirmed in a preliminary evaluation using software-and hardware-based implementations of the 842 compression algorithm.
KW  - Data compression
KW  - hardware
KW  - data transfer
KW  - accelerator architectures
Y1  - 2018
SN  - 978-1-5386-9184-7
U6  - https://doi.org/10.1109/CANDARW.2018.00031
SP  - 125
EP  - 131
PB  - IEEE
CY  - New York
ER  - 
TY  - GEN
A1  - Plauth, Max
A1  - Sterz, Christoph
A1  - Eberhardt, Felix
A1  - Feinbube, Frank
A1  - Polze, Andreas
T1  - Assessing NUMA performance based on hardware event counters
T2  - IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
N2  - Cost models play an important role for the efficient implementation of software systems. These models can be embedded in operating systems and execution environments to optimize execution at run time. Even though non-uniform memory access (NUMA) architectures are dominating today's server landscape, there is still a lack of parallel cost models that represent NUMA system sufficiently. Therefore, the existing NUMA models are analyzed, and a two-step performance assessment strategy is proposed that incorporates low-level hardware counters as performance indicators. To support the two-step strategy, multiple tools are developed, all accumulating and enriching specific hardware event counter information, to explore, measure, and visualize these low-overhead performance indicators. The tools are showcased and discussed alongside specific experiments in the realm of performance assessment.
KW  - Parallel programming
KW  - Performance analysis
KW  - Memory management
Y1  - 2017
SN  - 978-0-7695-6149-3
U6  - https://doi.org/10.1109/IPDPSW.2017.51
SN  - 2164-7062
SP  - 904
EP  - 913
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  -