TY  - JOUR
A1  - Krstić, Miloš
A1  - Weidling, Stefan
A1  - Petrovic, Vladimir
A1  - Sogomonyan, Egor S.
T1  - Enhanced architectures for soft error detection and correction in combinational and sequential circuits
JF  - Microelectronics reliability
N2  - In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28% lower than the TMR. (C) 2015 Elsevier Ltd. All rights reserved.
KW  - Soft errors
KW  - Combinational logic
KW  - DMR
KW  - TMR
KW  - Predictor
KW  - Self-checking
KW  - Concurrent checking
KW  - Timing errors
KW  - Transient faults
Y1  - 2016
U6  - https://doi.org/10.1016/j.microrel.2015.10.022
SN  - 0026-2714
VL  - 56
SP  - 212
EP  - 220
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Krstić, Miloš
A1  - Weidling, Stefan
A1  - Petrovic, Vladimir
A1  - Sogomonyan, Egor S.
T1  - Enhanced architectures for soft error detection and correction in combinational and sequential circuits
JF  - Microelectronics Reliability
N2  - In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.
Y1  - 2016
SN  - 0026-2714
VL  - 56
SP  - 212
EP  - 220
ER  -