TY  - GEN
A1  - Andjelkovic, Marko
A1  - Babic, Milan
A1  - Li, Yuanqing
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Kraemer, Rolf
T1  - Use of decoupling cells for mitigation of SET effects in CMOS combinational gates
T2  - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
N2  - This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles.
KW  - decoupling cells
KW  - radiation hardening
KW  - SET effects
KW  - CMOS technology
KW  - combinational logic
Y1  - 2019
SN  - 978-1-5386-9562-3
U6  - https://doi.org/10.1109/ICECS.2018.8617996
SP  - 361
EP  - 364
PB  - IEEE
CY  - New York
ER  -