TY  - JOUR
A1  - Bobda, Christophe
A1  - Yonga, Franck
A1  - Gebser, Martin
A1  - Ishebabi, Harold
A1  - Schaub, Torsten H.
T1  - High-level synthesis of on-chip multiprocessor architectures based on answer set programming
JF  - Journal of Parallel and Distributed Computing
N2  - We present a system-level synthesis approach for heterogeneous multi-processor on chip, based on Answer Set Programming(ASP). Starting with a high-level description of an application, its timing constraints and the physical constraints of the target device, our goal is to produce the optimal computing infrastructure made of heterogeneous processors, peripherals, memories and communication components. Optimization aims at maximizing speed, while minimizing chip area. Also, a scheduler must be produced that fulfills the real-time requirements of the application. Even though our approach will work for application specific integrated circuits, we have chosen FPGA as target device in this work because of their reconfiguration capabilities which makes it possible to explore several design alternatives. This paper addresses the bottleneck of problem representation size by providing a direct and compact ASP encoding for automatic synthesis that is semantically equivalent to previously established ILP and ASP models. We describe a use-case in which designers specify their applications in C/C++ from which optimum systems can be derived. We demonstrate the superiority of our approach toward existing heuristics and exact methods with synthesis results on a set of realistic case studies. (C) 2018 Elsevier Inc. All rights reserved.
KW  - System design
KW  - Architecture synthesis
KW  - Answer set programming
KW  - Multi-objective optimization
KW  - Technology mapping
KW  - Reconfigurable architecture
Y1  - 2018
U6  - https://doi.org/10.1016/j.jpdc.2018.02.010
SN  - 0743-7315
SN  - 1096-0848
VL  - 117
SP  - 161
EP  - 179
PB  - Elsevier
CY  - San Diego
ER  -