TY - JOUR A1 - Saposhnikov, Vl. V. V. V. A1 - Moshanin, Vl. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Experimental results for self-dual multi-output combinational circuits Y1 - 1999 ER - TY - JOUR A1 - Saposhnikov, Vl. V. A1 - Ocheretnij, V. A1 - Saposhnikov, V. V. A1 - Gössel, Michael T1 - Modified TMR-system with reduced hardware overhead Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael A1 - Sogomonyan, Egor S. T1 - New totally self-checking ripple and carry look-ahead adders Y1 - 1999 ER - TY - JOUR A1 - Gössel, Michael T1 - A new method of redundancy addition for circuit optimization JF - Preprint / Universität Potsdam, Institut für Informatik Y1 - 1999 SN - 0946-7580 VL - 1999, 08 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Dimitriev, Alexej A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Gössel, Michael T1 - Concurrent checking of sequential circuits by alternating inputs Y1 - 1999 ER - TY - JOUR A1 - Morosov, Andrej A1 - Gössel, Michael A1 - Hartje, Hendrik T1 - Reduced area overhead of the input party for code-disjoint circuits Y1 - 1999 ER - TY - JOUR A1 - Seuring, Markus A1 - Gössel, Michael T1 - A structural method for output compaction of sequential automata implemented as circuits Y1 - 1999 ER - TY - JOUR A1 - Bhattacharya, M. K. A1 - Dimitriev, Alexej A1 - Gössel, Michael T1 - Zero-aliasing space compresion using a single periodic output and its application to testing of embedded Y1 - 2000 ER - TY - BOOK A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - A new self-checking sum-bit duplicated carry-select adder T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2003 SN - 0946-7580 VL - 2003, 5 PB - Univ. CY - Potsdam ER - TY - BOOK A1 - Wu, K. A1 - Karri, R. A1 - Kuznetsov, Grigory A1 - Gössel, Michael T1 - Low Cost Concurrent Error Detection for the Advanced Encryption Standart T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2003 SN - 0946-7580 VL - 2003, 8 PB - Univ. CY - Potsdam ER - TY - BOOK A1 - Saposhnikov, V. V. A1 - Saposhnikov, Vl. V. A1 - Morozov, Alexei A1 - Gössel, Michael T1 - Necessary and Sufficient Conditions for the Existence of Self-Checking Circuits ba Use of Complementary Circuits T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2004 SN - 0946-7580 VL - 2004, 1 PB - Univ. CY - Potsdam ER - TY - BOOK A1 - Marienfeld, Daniel A1 - Sogomonyan, Egor S. A1 - Ocheretnij, V. A1 - Gössel, Michael T1 - Self-checking Output-duplicated Booth-2 Multiplier T3 - Preprint / Universität Potsdam, Institut für Informatik Y1 - 2005 SN - 0946-7580 VL - 2005, 1 PB - Univ. CY - Potsdam ER - TY - JOUR A1 - Ocheretnij, Vitalij A1 - Gössel, Michael A1 - Sogomonyan, Egor S. A1 - Marienfeld, Daniel T1 - Modulo p=3 checking for a carry select adder N2 - In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks Y1 - 2006 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-006-6260-8 ER - TY - JOUR A1 - Hilscher, Martin A1 - Braun, Michael A1 - Richter, Michael A1 - Leininger, Andreas A1 - Gössel, Michael T1 - X-tolerant test data compaction with accelerated shift registers N2 - Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution. Y1 - 2009 UR - http://www.springerlink.com/content/100286 U6 - https://doi.org/10.1007/s10836-009-5107-5 SN - 0923-8174 ER - TY - JOUR A1 - Rabenalt, Thomas A1 - Richter, Michael A1 - Pöhl, Frank A1 - Gössel, Michael T1 - Highly efficient test response compaction using a hierarchical x-masking technique JF - IEEE transactions on computer-aided design of integrated circuits and systems N2 - This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x. KW - Design for testability (DFT) KW - test response compaction KW - X-masking KW - X-values Y1 - 2012 U6 - https://doi.org/10.1109/TCAD.2011.2181847 SN - 0278-0070 VL - 31 IS - 6 SP - 950 EP - 957 PB - Inst. of Electr. and Electronics Engineers CY - Piscataway ER -