TY - JOUR A1 - Wist, Dominic A1 - Wollowski, Ralf A1 - Schaefer, Mark A1 - Vogler, Walter T1 - Avoiding irreducible CSC conflicts by internal communication N2 - Resynthesis of handshake specifications obtained e. g. from BALSA or TANGRAM with speed-independent logic synthesis from STGs is a promising approach. To deal with state-space explosion, we suggested STG decomposition; a problem is that decomposition can lead to irreducible CSC conflicts. Here, we present a new approach to solve such conflicts by introducing internal communication between the components. We give some first, very encouraging results for very large STGs concerning synthesis time and circuit area. Y1 - 2009 UR - http://iospress.metapress.com/content/300178/ U6 - https://doi.org/10.3233/Fi-2009-140 SN - 0169-2968 ER - TY - JOUR A1 - Wist, Dominic A1 - Schaefer, Mark A1 - Vogler, Walter A1 - Wollowski, Ralf T1 - Signal transition graph decomposition internal communication for speed independent circuit implementation JF - IET Computers and digital techniques N2 - Logic synthesis of speed independent circuits based on signal transition graph (STG) decomposition is a promising approach to tackle complexity problems like state-space explosion. Unfortunately, decomposition can result in components that in isolation have irreducible complete state coding conflicts. In earlier work, the authors showed how to resolve such conflicts by introducing internal communication between components, but only for very restricted specification structures. Here, they improve their former work by presenting algorithms for identifying delay transitions and inserting gyroscopes for specifications having a much more general structure. Thus, the authors are now able to synthesise controllers from real-life specifications. For all algorithms, they present correctness proofs and show their successful application to benchmarks, including very complex STGs arising in the context of control resynthesis. Y1 - 2011 U6 - https://doi.org/10.1049/iet-cdt.2010.0162 SN - 1751-8601 VL - 5 IS - 6 SP - 440 EP - 451 PB - Institution of Engineering and Technology CY - Hertford ER - TY - BOOK A1 - Wist, Dominic A1 - Wollowski, Ralf T1 - STG decomposition : avoiding irreducible CSC conflicts by internal communication N2 - Inhalt: 1 Introduction 2 Basic Definitions 3 Achieving SI Implementability by Internal Communication 4 Towards a Structural Method 5 Examples 6 Conclusions and Future Work T3 - Technische Berichte des Hasso-Plattner-Instituts für Digital Engineering an der Universität Potsdam - 20 Y1 - 2007 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:517-opus-32968 SN - 978-3-940793-02-7 ER - TY - BOOK A1 - Wist, Dominic A1 - Schaefer, Mark A1 - Vogler, Walter A1 - Wollowski, Ralf T1 - STG decomposition : internal communication for SI implementability N2 - STG decomposition is a promising approach to tackle the complexity problems arising in logic synthesis of speed independent circuits, a robust asynchronous (i.e. clockless) circuit type. Unfortunately, STG decomposition can result in components that in isolation have irreducible CSC conflicts. Generalising earlier work, it is shown how to resolve such conflicts by introducing internal communication between the components via structural techniques only. N2 - STG-Dekomposition ist ein bewährter Ansatz zur Bewältigung der Komplexitätsprobleme bei der Logiksynthese von SI (speed independent) Schaltungen – ein robuster asynchroner (d.h. ohne Taktsignal arbeitender digitaler) Schaltungstyp. Allerdings können dabei Komponenten mit irreduziblen CSC-Konflikten entstehen. Durch Verallgemeinerung früherer Arbeiten wird gezeigt, wie solche Konflikte durch Einführung interner Kommunikation zwischen den Komponenten gelöst werden können, und zwar ausschließlich durch Verwendung an der Graphenstruktur ansetzender Verfahren. T3 - Technische Berichte des Hasso-Plattner-Instituts für Digital Engineering an der Universität Potsdam - 32 KW - Asynchrone Schaltung KW - Petrinetz KW - Signalflankengraph (SFG oder STG) KW - STG-Dekomposition KW - speed independent KW - CSC KW - Controller-Resynthese KW - Asynchronous circuit KW - petri net KW - signal transition graph KW - STG decomposition KW - speed independent KW - CSC KW - control resynthesis Y1 - 2010 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:517-opus-40786 SN - 978-3-86956-037-3 PB - Universitätsverlag Potsdam CY - Potsdam ER - TY - JOUR A1 - Khomenko, Victor A1 - Schäfer, Mark A1 - Vogler, Walter A1 - Wollowski, Ralf T1 - STG decomposition strategies in combination with unfolding N2 - For synthesising efficient asynchronous circuits one has to deal with the state space explosion problem. In order to alleviate this problem one can decompose the STG into smaller components. This paper deals with the decomposition method of Vogler and Wollowski and introduces several strategies for its efficient implementations. Furthermore, this approach is combined with another method to alleviate state space explosion, which is based on Petri net unfoldings. The developed algorithms are compared by means of benchmark examples, and the experimental results show significant improvement in terms of memory usage and runtime compared with other existing methods. Y1 - 2009 UR - http://www.springerlink.com/content/100460 U6 - https://doi.org/10.1007/s00236-009-0102-y SN - 0001-5903 ER -