TY  - GEN
A1  - Tala, Mahdi
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Bertozzi, Davide
T1  - Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip
T2  - XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)
N2  - The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance.
Y1  - 2018
SN  - 978-1-7281-0171-2
U6  - https://doi.org/10.1109/DCIS.2018.8681461
SN  - 2471-6170
SN  - 2640-5563
PB  - IEEE
CY  - New York
ER  - 
TY  - GEN
A1  - Schrape, Oliver
A1  - Balashov, Alexey
A1  - Simevski, Aleksandar
A1  - Benito, Carlos
A1  - Krstić, Miloš
T1  - Master-Clone placement with individual clock tree implementation
BT  - a Case on Physical Chip Design
T2  - 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
N2  - A hybrid design approach of the hierarchical physical implementation design flow is presented and demonstrated on a fault-tolerant low-power multiprocessor system. The proposed flow allows to implement selected submodules in parallel with contrary requirements such as identical placement and individual block implementation. The overall system contains four Leon2 cores and communicates via the Waterbear framework and supports Adaptive Voltage Scaling (AVS) functionality. Three of the processor core variants are derived from the first baseline reference core but implemented individually at block level based on their clock tree specification. The chip is prepared for space applications and designed with triple modular redundancy (TMR) for control parts. The low-power performance is enabled by contemporary power and clock management control. An ASIC is fabricated in a low-power 0.13 mu m BiCMOS technology process node.
KW  - Hierarchical Design
KW  - Physical Implementation
KW  - Clock Tree Implementation
Y1  - 2018
SN  - 978-1-5386-7656-1
PB  - IEEE
CY  - New York
ER  - 
TY  - JOUR
A1  - Schrape, Oliver
A1  - Andjelkovic, Marko
A1  - Breitenreiter, Anselm
A1  - Zeidler, Steffen
A1  - Balashov, Alexey
A1  - Krstić, Miloš
T1  - Design and evaluation of radiation-hardened standard cell flip-flops
JF  - IEEE transactions on circuits and systems : a publication of the IEEE Circuits and Systems Society: 1, Regular papers
N2  - Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV.cm(2)/mg) to (62.5 MeV.cm(2)/mg), depending on the variant.
KW  - Single event effect
KW  - fault tolerance
KW  - triple modular redundancy
KW  - ASIC
KW  - design flow
KW  - radhard design
Y1  - 2021
U6  - https://doi.org/10.1109/TCSI.2021.3109080
SN  - 1549-8328
SN  - 1558-0806
SN  - 1057-7122
VL  - 68
IS  - 11
SP  - 4796
EP  - 4809
PB  - Inst. of Electr. and Electronics Engineers
CY  - New York, NY
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Chen, Li
A1  - Nofal, Issam
A1  - Chen, Mo
A1  - Wang, Haibin
A1  - Liu, Rui
A1  - Chen, Qingyu
A1  - Krstić, Miloš
A1  - Shi, Shuting
A1  - Guo, Gang
A1  - Baeg, Sang H.
A1  - Wen, Shi-Jie
A1  - Wong, Richard
T1  - Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree
JF  - Microelectronics reliability
N2  - The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.
KW  - Clock tree
KW  - Modeling
KW  - Single-event transient (SET)
Y1  - 2018
U6  - https://doi.org/10.1016/j.microrel.2018.05.016
SN  - 0026-2714
VL  - 87
SP  - 24
EP  - 32
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Li, Yuanqing
A1  - Breitenreiter, Anselm
A1  - Andjelkovic, Marko
A1  - Chen, Junchao
A1  - Babic, Milan
A1  - Krstić, Miloš
T1  - Double cell upsets mitigation through triple modular redundancy
JF  - Microelectronics Journal
N2  - A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.
KW  - Triple modular redundancy (TMR)
KW  - Double cell upsets (DCUs)
Y1  - 2019
U6  - https://doi.org/10.1016/j.mejo.2019.104683
SN  - 0026-2692
SN  - 1879-2391
VL  - 96
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Kuentzer, Felipe A.
A1  - Krstić, Miloš
T1  - Soft error detection and correction architecture for asynchronous bundled data designs
JF  - IEEE transactions on circuits and systems
N2  - In this paper, an asynchronous design for soft error detection and correction in combinational and sequential circuits is presented. The proposed architecture is called Asynchronous Full Error Detection and Correction (AFEDC). A custom design flow with integrated commercial EDA tools generates the AFEDC using the asynchronous bundled-data design style. The AFEDC relies on an Error Detection Circuit (EDC) for protecting the combinational logic and fault-tolerant latches for protecting the sequential logic. The EDC can be implemented using different detection methods. For this work, two boundary variants are considered, the Full Duplication with Comparison (FDC) and the Partial Duplication with Parity Prediction (PDPP). The AFEDC architecture can handle single events and timing faults of arbitrarily long duration as well as the synchronous FEDC, but additionally can address known metastability issues of the FEDC and other similar synchronous architectures and provide a more practical solution for handling the error recovery process. Two case studies are developed, a carry look-ahead adder and a pipelined non-restoring array divider. Results show that the AFEDC provides equivalent fault coverage when compared to the FEDC while reducing area, ranging from 9.6% to 17.6%, and increasing energy efficiency, which can be up to 6.5%.
KW  - circuit Faults
KW  - latches
KW  - Fault tolerance
KW  - Fault tolerant systems
KW  - timing
KW  - clocks
KW  - transient analysis
KW  - asynchrounous design
KW  - soft errors
KW  - transient Faults
KW  - bundled data
KW  - click controller
KW  - self-checking
KW  - concurrent checking
KW  - DMR
KW  - TMR
Y1  - 2020
U6  - https://doi.org/10.1109/TCSI.2020.2998911
SN  - 1549-8328
SN  - 1558-0806
VL  - 67
IS  - 12
SP  - 4883
EP  - 4894
PB  - Institute of Electrical and Electronics Engineers
CY  - New York
ER  - 
TY  - JOUR
A1  - Kucharski, Maciej
A1  - Ergintav, Arzu
A1  - Ahmad, Wael Abdullah
A1  - Krstić, Miloš
A1  - Ng, Herman Jalli
A1  - Kissinger, Dietmar
T1  - A Scalable 79-GHz Radar Platform Based on Single-Channel Transceivers
JF  - IEEE Transactions on Microwave Theory and Techniques
N2  - This paper presents a scalable E-band radar platform based on single-channel fully integrated transceivers (TRX) manufactured using 130-nm silicon-germanium (SiGe) BiCMOS technology. The TRX is suitable for flexible radar systems exploiting massive multiple-input-multipleoutput (MIMO) techniques for multidimensional sensing. A fully integrated fractional-N phase-locked loop (PLL) comprising a 39.5-GHz voltage-controlled oscillator is used to generate wideband frequency-modulated continuous-wave (FMCW) chirp for E-band radar front ends. The TRX is equipped with a vector modulator (VM) for high-speed carrier modulation and beam-forming techniques. A single TRX achieves 19.2-dBm maximum output power and 27.5-dB total conversion gain with input-referred 1-dB compression point of -10 dBm. It consumes 220 mA from 3.3-V supply and occupies 3.96 mm(2) silicon area. A two-channel radar platform based on full-custom TRXs and PLL was fabricated to demonstrate high-precision and high-resolution FMCW sensing. The radar enables up to 10-GHz frequency ramp generation in 74-84-GHz range, which results in 1.5-cm spatial resolution. Due to high output power, thus high signal-to-noise ratio (SNR), a ranging precision of 7.5 mu m for a target at 2 m was achieved. The proposed architecture supports scalable multichannel applications for automotive FMCW using a single local oscillator (LO).
KW  - Automotive
KW  - E-band
KW  - frequency-modulated continuous-wave (FMCW)
KW  - patch antenna
KW  - phase-locked loop (PLL)
KW  - power amplifier (PA)
KW  - radar
KW  - scalable
KW  - transceiver (TRX)
Y1  - 2019
U6  - https://doi.org/10.1109/TMTT.2019.2914104
SN  - 0018-9480
SN  - 1557-9670
VL  - 67
IS  - 9
SP  - 3882
EP  - 3896
PB  - Inst. of Electr. and Electronics Engineers
CY  - Piscataway
ER  - 
TY  - JOUR
A1  - Krstić, Miloš
A1  - Weidling, Stefan
A1  - Petrovic, Vladimir
A1  - Sogomonyan, Egor S.
T1  - Enhanced architectures for soft error detection and correction in combinational and sequential circuits
JF  - Microelectronics reliability
N2  - In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master-slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26-28% lower than the TMR. (C) 2015 Elsevier Ltd. All rights reserved.
KW  - Soft errors
KW  - Combinational logic
KW  - DMR
KW  - TMR
KW  - Predictor
KW  - Self-checking
KW  - Concurrent checking
KW  - Timing errors
KW  - Transient faults
Y1  - 2016
U6  - https://doi.org/10.1016/j.microrel.2015.10.022
SN  - 0026-2714
VL  - 56
SP  - 212
EP  - 220
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Krstić, Miloš
A1  - Weidling, Stefan
A1  - Petrovic, Vladimir
A1  - Sogomonyan, Egor S.
T1  - Enhanced architectures for soft error detection and correction in combinational and sequential circuits
JF  - Microelectronics Reliability
N2  - In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.
Y1  - 2016
SN  - 0026-2714
VL  - 56
SP  - 212
EP  - 220
ER  - 
TY  - GEN
A1  - Krstić, Miloš
A1  - Jentzsch, Anne-Kristin
T1  - Reliability, safety and security of the electronics in automated driving vehicles - joint lab lecturing approach
T2  - 2018 12TH European Workshop on Microelectronics Education (EWME)
N2  - This paper proposes an education approach for master and bachelor students to enhance their skills in the area of reliability, safety and security of the electronic components in automated driving. The approach is based on the active synergetic work of research institutes, academia and industry in the frame of joint lab. As an example, the jointly organized summer school with the respective focus is organized and elaborated.
KW  - reliability
KW  - safety
KW  - security
KW  - automated driving
KW  - joint lab
Y1  - 2018
SN  - 978-1-5386-1157-9
SP  - 21
EP  - 22
PB  - IEEE
CY  - New York
ER  - 
TY  - JOUR
A1  - Fan, Xin
A1  - Stegmann, Mikkel B.
A1  - Schrappe, Oliver
A1  - Zeidler, Steffen
A1  - Jensen, Isac G.
A1  - Thorsen, Jannich
A1  - Bjerregaard, Tobias
A1  - Krstić, Miloš
T1  - Frequency-domain optimization of digital switching noise based on clock scheduling
JF  - IEEE Transactions on Circuits and Systems I
N2  - The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms of noise power, a two-phase clocking scheme is employed for system timing. Second, on-chip clock latencies are manipulated to target harmonic peaks in specific frequency bands for the spectral noise optimization. An automated design flow, which allows for noise optimization in user-defined application-specific frequency bands, is developed. The effectiveness of our design solution is validated by measurements of substrate noise and conductive EMI (electromagnetic interference) noise on a test chip, which consists of four wireless sensor node baseband processors each addressing a distinct clock-tree-synthesis strategy. Compared to the reference synchronous design, the proposed clock scheduling solution substantially reduces noise in the target GSM-850 band, i.e., by 11.1 dB on the substrate noise and 12.9 dB on the EMI noise, along with dramatic noise peak drops measured at the 50-MHz clock frequency.
Y1  - 2016
U6  - https://doi.org/10.1109/TCSI.2016.2546118
SN  - 1549-8328
VL  - 63
IS  - 7
SP  - 982
EP  - 993
ER  - 
TY  - JOUR
A1  - Dug, Mehmed
A1  - Weidling, Stefan
A1  - Sogomonyan, Egor
A1  - Jokic, Dejan
A1  - Krstić, Miloš
T1  - Full error detection and correction method applied on pipelined structure using two approaches
JF  - Journal of circuits, systems and computers
N2  - In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.
KW  - Fault tolerance
KW  - FEDC
KW  - EDC
Y1  - 2020
U6  - https://doi.org/10.1142/S0218126620502187
SN  - 0218-1266
SN  - 1793-6454
VL  - 29
IS  - 13
PB  - World Scientific
CY  - Singapore
ER  - 
TY  - JOUR
A1  - Chen, Junchao
A1  - Lange, Thomas
A1  - Andjelkovic, Milos
A1  - Simevski, Aleksandar
A1  - Krstić, Miloš
T1  - Prediction of solar particle events with SRAM-based soft error rate monitor and supervised machine learning
JF  - Microelectronics reliability
N2  - This work introduces an embedded approach for the prediction of Solar Particle Events (SPEs) in space applications by combining the real-time Soft Error Rate (SER) measurement with SRAM-based detector and the offline trained machine learning model. The proposed approach is intended for the self-adaptive fault-tolerant multiprocessing systems employed in space applications. With respect to the state-of-the-art, our solution allows for predicting the SER 1 h in advance and fine-grained hourly tracking of SER variations during SPEs as well as under normal conditions. Therefore, the target system can activate the appropriate mechanisms for radiation hardening before the onset of high radiation levels. Based on the comparison of five different machine learning algorithms trained with the public space flux database, the preliminary results indicate that the best prediction accuracy is achieved with the recurrent neural network (RNN) with long short-term memory (LSTM).
Y1  - 2020
U6  - https://doi.org/10.1016/j.microrel.2020.113799
SN  - 0026-2714
VL  - 114
PB  - Elsevier
CY  - Oxford
ER  - 
TY  - JOUR
A1  - Breitenreiter, Anselm
A1  - Andjelković, Marko
A1  - Schrape, Oliver
A1  - Krstić, Miloš
T1  - Fast error propagation probability estimates by answer set programming and approximate model counting
JF  - IEEE Access
N2  - We present a method employing Answer Set Programming in combination with Approximate Model Counting for fast and accurate calculation of error propagation probabilities in digital circuits. By an efficient problem encoding, we achieve an input data format similar to a Verilog netlist so that extensive preprocessing is avoided. By a tight interconnection of our application with the underlying solver, we avoid iterating over fault sites and reduce calls to the solver. Several circuits were analyzed with varying numbers of considered cycles and different degrees of approximation. Our experiments show, that the runtime can be reduced by approximation by a factor of 91, whereas the error compared to the exact result is below 1%.
KW  - Circuit faults
KW  - Integrated circuit modeling
KW  - Programming
KW  - Analytical models
KW  - Search problems
KW  - Flip-flops
KW  - Encoding
KW  - Answer set programming
KW  - approximate model counting
KW  - error propagation
KW  - radhard design
KW  - reliability analysis
KW  - selective fault tolerance
KW  - single event upsets
Y1  - 2022
U6  - https://doi.org/10.1109/ACCESS.2022.3174564
SN  - 2169-3536
VL  - 10
SP  - 51814
EP  - 51825
PB  - Inst. of Electr. and Electronics Engineers
CY  - Piscataway
ER  - 
TY  - JOUR
A1  - Andjelković, Marko
A1  - Chen, Junchao
A1  - Simevski, Aleksandar
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Kraemer, Rolf
T1  - Monitoring of particle count rate and LET variations with pulse stretching inverters
JF  - IEEE transactions on nuclear science : a publication of the IEEE Nuclear and Plasma Sciences Society
N2  - This study investigates the use of pulse stretching (skew-sized) inverters for monitoring the variation of count rate and linear energy transfer (LET) of energetic particles. The basic particle detector is a cascade of two pulse stretching inverters, and the required sensing area is obtained by connecting up to 12 two-inverter cells in parallel and employing the required number of parallel arrays. The incident particles are detected as single-event transients (SETs), whereby the SET count rate denotes the particle count rate, while the SET pulsewidth distribution depicts the LET variations. The advantage of the proposed solution is the possibility to sense the LET variations using fully digital processing logic. SPICE simulations conducted on IHP's 130-nm CMOS technology have shown that the SET pulsewidth varies by approximately 550 ps over the LET range from 1 to 100 MeV center dot cm(2) center dot mg(-1). The proposed detector is intended for triggering the fault-tolerant mechanisms within a self-adaptive multiprocessing system employed in space. It can be implemented as a standalone detector or integrated in the same chip with the target system.
KW  - Particle detector
KW  - pulse stretching inverters
KW  - single-event transient
KW  - (SET) count rate
KW  - SET pulsewidth distribution
Y1  - 2021
U6  - https://doi.org/10.1109/TNS.2021.3076400
SN  - 0018-9499
SN  - 1558-1578
VL  - 68
IS  - 8
SP  - 1772
EP  - 1781
PB  - Institute of Electrical and Electronics Engineers
CY  - New York, NY
ER  - 
TY  - GEN
A1  - Andjelkovic, Marko
A1  - Babic, Milan
A1  - Li, Yuanqing
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Kraemer, Rolf
T1  - Use of decoupling cells for mitigation of SET effects in CMOS combinational gates
T2  - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
N2  - This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles.
KW  - decoupling cells
KW  - radiation hardening
KW  - SET effects
KW  - CMOS technology
KW  - combinational logic
Y1  - 2019
SN  - 978-1-5386-9562-3
U6  - https://doi.org/10.1109/ICECS.2018.8617996
SP  - 361
EP  - 364
PB  - IEEE
CY  - New York
ER  -