TY  - GEN
A1  - Andjelkovic, Marko
A1  - Babic, Milan
A1  - Li, Yuanqing
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Kraemer, Rolf
T1  - Use of decoupling cells for mitigation of SET effects in CMOS combinational gates
T2  - 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
N2  - This paper investigates the applicability of CMOS decoupling cells for mitigating the Single Event Transient (SET) effects in standard combinational gates. The concept is based on the insertion of two decoupling cells between the gate's output and the power/ground terminals. To verify the proposed hardening approach, extensive SPICE simulations have been performed with standard combinational cells designed in IHP's 130 nm bulk CMOS technology. Obtained simulation results have shown that the insertion of decoupling cells results in the increase of the gate's critical charge, thus reducing the gate's soft error rate (SER). Moreover, the decoupling cells facilitate the suppression of SET pulses propagating through the gate. It has been shown that the decoupling cells may be a competitive alternative to gate upsizing and gate duplication for hardening the gates with lower critical charge and multiple (3 or 4) inputs, as well as for filtering the short SET pulses induced by low-LET particles.
KW  - decoupling cells
KW  - radiation hardening
KW  - SET effects
KW  - CMOS technology
KW  - combinational logic
Y1  - 2019
SN  - 978-1-5386-9562-3
U6  - https://doi.org/10.1109/ICECS.2018.8617996
SP  - 361
EP  - 364
PB  - IEEE
CY  - New York
ER  - 
TY  - GEN
A1  - Tala, Mahdi
A1  - Schrape, Oliver
A1  - Krstić, Miloš
A1  - Bertozzi, Davide
T1  - Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip
T2  - XXXIII Conference on Design of Circuits and Integrated Systems (DCIS)
N2  - The relentless improvement of silicon photonics is making optical interconnects and networks appealing for use in miniaturized systems, where electrical interconnects cannot keep up with the growing levels of core integration due to bandwidth density and power efficiency limitations. At the same time, solutions such as 3D stacking or 2.5D integration open the door to a fully dedicated process optimization for the photonic die. However, an architecture-level integration challenge arises between the electronic network and the optical one in such tightly-integrated parallel systems. It consists of adapting signaling rates, matching the different levels of communication parallelism, handling cross-domain flow control, addressing re-synchronization concerns, and avoiding protocol-dependent deadlock. The associated energy and performance overhead may offset the inherent benefits of the emerging technology itself. This paper explores a hybrid CMOS-ECL bridge architecture between 3D-stacked technology-heterogeneous networks-on-chip (NoCs). The different ways of overcoming the serialization challenge (i.e., through an improvement of the signaling rate and/or through space-/wavelength division multiplexing options) give rise to a configuration space that the paper explores, in search for the most energy-efficient configuration for high-performance.
Y1  - 2018
SN  - 978-1-7281-0171-2
U6  - https://doi.org/10.1109/DCIS.2018.8681461
SN  - 2471-6170
SN  - 2640-5563
PB  - IEEE
CY  - New York
ER  -